F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

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ID 683886
Date 10/07/2024
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon® Streaming Intel FPGA IP for PCI Express : IP Core v12.2.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express: IP Core v12.1.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v12.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.13. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.14. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.15. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0

Table 5.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v10.0.0 : 2023.10.03
Quartus® Prime Version Description Impact
23.3

TLP Bypass downstream mode support is enabled for PCIe Gen3 1x4 interface.

You can use 4 lanes of F-Tile to implement PCIe configuration as mentioned in the description while the remaining lanes are used for Ethernet/PMA Direct.

New Analog Parameter tab has been created in the IP GUI for lowloss parameter setting.

The transceiver analog settings are enabled for low loss PCIe design.

This parameter should only be enabled for chip-to-chip design where the insertion loss from endpoint silicon pad to root port silicon pad including the package insertion loss is below 8 dB at 8 GHz.

This parameter tab replaces the analog settings that were previously set through QSF file.

Fixed FASTSIM simulation errors and limitation seen in previous IP release.

FASTSIM is now available for all simulators.

You can use FASTSIM to simulate the IP without fatal error.

Fixed compilation errors when the IP is generated in VHDL format.

You can generate the IP in VHDL format without compilation errors.
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