F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

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ID 683886
Date 10/07/2024
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon® Streaming Intel FPGA IP for PCI Express : IP Core v12.2.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express: IP Core v12.1.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v12.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.13. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.14. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.15. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0

Table 11.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v5.0.0 : 2022.03.28
Quartus® Prime Version Description Impact
22.1

Added independent refclk support for 2x4 Hard IP Mode

F-Tile PCIe IP can now be used to connect two discrete x4 PCIe endpoints where the independent refclk source is required.

Debug Toolkit bug fixes for BAR information and PHY lane refresh issue of PCIe 1 x4 configuration (Topology H).

Use Debug Toolkit from Quartus® Prime Pro Edition 22.1 to avoid incorrect BAR information and issue with PCIe 1 x4 configuration (Topology H).

Added independent PERST feature for port bifurcation support.

Design requires bifurcated PCIe links to operate independently to each other can now be supported by F-Tile PCIe IP with the independent PERST and refclk feature.

Warning messages clean-up for the F-Tile Avalon-ST PCIe Hard IP

Allows users to focus on warning messages that require their attention.

Added 450 MHz PLD clock frequency option and -3 FPGA fabric speed grade support

No impact to existing user other than additional option for PLD clock frequency and FPGA fabric speed grade option

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