F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

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ID 683886
Date 10/07/2024
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1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon® Streaming Intel FPGA IP for PCI Express : IP Core v12.2.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express: IP Core v12.1.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v12.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.13. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.14. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.15. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0

Table 9.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v7.0.0 : 2022.10.04
Quartus® Prime Version Description Impact
22.3

Added Agilex™ 7 F-Series F-Tile ES FPGA Development Kit board preset for design example generation.

The VID-related settings including the pin assignments are included in the .qsf file of the generated design example when selected.

Introduced Clock Divider option in the F-Tile Avalon-ST IP Parameter Editor.

An additional IOPLL is used for IP configuration with PLD Clock Frequency at 250 MHz or below for Gen4 x16 or Gen4 2x8 Hard IP Modes.

Clock Divider option is available for single tile usage to reclaim the IOPLL for other applications.

Added FASTSIM mode support for the F-Tile Avalon-ST IP for PCI Express configured in Root Port mode.

Allow users to use FASTSIM mode for F-Tile Avalon-ST IP for PCI Express configured in Root Port mode to shorten the simulation time.

Fixed the issue where the F-Tile Avalon-ST IP for PCI Express does not respond to Configuration TLPs with a CRS (Config Retry Status) when CvP is not enabled.

Autonomous Hard IP and p#_app_req_retry_en_i signal are now working correctly when CvP is disabled in the F-Tile Avalon-ST IP Parameter Editor.

Added the Eye Viewer feature in the Debug Toolkit while in Endpoint mode and using Linux OS and Windows.

Allows users to measure on-die eye height margin.

Added configurable payload size support for the F-Tile Performance design example variant.

Allow users to run throughput test with different payload size.
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