F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

Download PDF
ID 683886
Date 10/07/2024
Public
Document Table of Contents
Document Table of Contents x
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes x
1.1. F-Tile Avalon® Streaming Intel FPGA IP for PCI Express : IP Core v12.2.0 1.2. F-Tile Avalon Streaming Intel FPGA IP for PCI Express: IP Core v12.1.0 1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v12.0.0 1.4. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0 1.5. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v10.0.0 1.6. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v9.0.0 1.7. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.1.0 1.8. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v8.0.0 1.9. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v7.0.0 1.10. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v6.0.0 1.11. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v5.0.0 1.12. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v4.0.0 1.13. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v3.0.0 1.14. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v2.0.0 1.15. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : User Guide Archives
1. F-Tile Avalon Streaming Intel FPGA IP for PCI Express* Release Notes

1.1. F-Tile Avalon® Streaming Intel FPGA IP for PCI Express : IP Core v12.2.0

Table 1.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v12.2.0 : 2024.10.07
Quartus® Prime Version Description Impact
24.3

Starting with the Quartus® Prime Pro Edition software version 23.4, the software enforces a check for the appropriate .qsf assignment required to constrain the device’s OSC_CLK_1 pin for projects which contain transceivers in the design.

A new parameter, Device Initialization Clock, is introduced under the Example Designs tab of the IP Parameter Editor. This parameter allows you to set the frequency of the OSC_CLK_1 pin to match your board design for design example generation.

You must provide the .qsf assignment in your design that contains the F-Tile Avalon® Streaming Intel FPGA IP for PCI Express in order to compile the design successfully in the Quartus® Prime Pro Edition software.

The issue with the Endpoint acceptable latency value selection for L0s and L1 link states under the Power Management tab of the IP Parameter Editor has been fixed in this release. You can now change the Endpoint acceptable latency value for L0s and L1 link states to the supported values other than the default value.
Level Two Title