F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* Release Notes

ID 683886
Date 7/08/2024
Public

1.3. F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP Core v11.0.0

Table 3.  F-Tile Avalon Streaming Intel FPGA IP for PCI Express : IP v11.0.0 : 2024.01.29
Quartus® Prime Version Description Impact
23.4

The default Gen 4 Requested equalization far-end TX preset vector is changed to P5/6/8/9(0x00000360) with P1 and P3 being removed compared to previous releases.

The equalization process of link training is expected to improve.

For simulation in PIPE mode, o_p1_prot_f2t_ssr[18:3] is available for users to generate PIPE reset to the VIP.

This allows users to reset the VIP during PIPE mode simulation.

Introduction of PCIe Receiver Detection new tab.

It is optional for the PCIe controller to ignore receiver detection from PHY during LTSSM Detect state and user-defined value.