AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Resolve Interface Requirements and Value Mismatches

In the Interface Requirements tab you can verify that the exported interfaces meet the interface requirements.

  1. Click the Interface Requirements tab in Platform Designer.

    The exported interfaces in the tutorial system appear in the Current System list. The Interface Requirements list shows the definition of the generic component. A green highlight indicates a missing item. A blue highlight indicates an item with parameter mismatches.

    Figure 33. Missing Components and Value Mismatches
  2. View the Interface Requirements list for missing items. What appears in the figure indicates a missing slave interface of the pipeline bridge. Fix the missing items by exporting the appropriate signal.
  3. In the System Contents tab, double-click the entry in the Export column corresponding to the s0 for the mm_bridge component and rename it to slave.
    Figure 34. Export and Rename Avalon-MM Slave
  4. Re-examine the Interface Requirements tab. The Current System list contains the slave interface with no green highlight. Next you resolve the different item highlighted in blue.
    Figure 35. Current System / Interface Requirement Value Mismatch
  5. Click the signal name highlighted in blue to display more information in the Parameter Differences pane. Typically, you change the Current System Value to match the Interface Requirement Value by editing the parameters of that component.
    Figure 36. Changing Current System Value
  6. Click read_master_readdata[32] and examine the Parameter Differences pane. In the top_system, the data width of the Avalon Memory Mapped Master of the EMIF controller is 256. The data width of the memory_tester_subsystem must match with a value of 256. Adapters inserted to handle data width mismatch may become the bottle-neck of a design.
  7. This exported interface comes from the Pattern Writer. To alter its width, alter the parameters of that IP core. To change the data width of Pattern Writer, double-click the pattern_writer component. Change the Data Width in the parameter editor to 256.
    Figure 37. Pattern Writer Settings Dialog Box

    Repeat the Step 7 for the pattern_reader component.

    Figure 38. Pattern Reader Settings Dialog Box

    These parameter changes alter the width of *_byteenable signals accordingly.

  8. Verify that your Interface Requirements tab contains no missing items or mismatched items. In cases where you want to keep the current system value, you can click the Copy button to copy items from the left table to the right.
    Figure 39. Completed Interface Requirements

    This completes the editing of component parameters to validate interface requirements.

  9. Save and close the project. There is no requirement to generate HDL because we are replacing the generic component in top_system.qsys with the implemented subsystem.

  10. Close Platform Designer and inspect the Files tab in the Project Navigator. Files for the memory_tester_subsystem are present in the Intel® Quartus® Prime Pro Edition project.

    Figure 40. Files List for memory_tester_subsystem.v
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