Visible to Intel only — GUID: bqb1488510818911
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
DLL Range Specifications
DQS Logic Block Specifications
Memory Output Clock Jitter Specifications
OCT Calibration Block Specifications
POR Specifications
JTAG Configuration Timing
FPP Configuration Timing
AS Configuration Timing
DCLK Frequency Specification in the AS Configuration Scheme
PS Configuration Timing
Initialization
Configuration Files
Minimum Configuration Time Estimation
Remote System Upgrades
User Watchdog Internal Circuitry Timing Specifications
Visible to Intel only — GUID: bqb1488510818911
Ixiasoft
Transceiver Power Supply Operating Conditions
Symbol | Description | Condition | Minimum 14 | Typical | Maximum 14 | Unit |
---|---|---|---|---|---|---|
VCCT_GXB[L1][C,D] | Transmitter power supply | Chip-to-chip ≤ 12.5 Gbps Or Backplane ≤ 6.6 Gbps |
1.0 | 1.03 | 1.06 | V |
Chip-to-chip ≤ 11.3 Gbps |
0.92 | 0.95 | 0.98 | V | ||
VCCR_GXB[L1][C,D] | Receiver power supply | Chip-to-chip ≤ 12.5 Gbps Or Backplane ≤ 6.6 Gbps |
1.0 | 1.03 | 1.06 | V |
Chip-to-chip ≤ 11.3 Gbps |
0.92 | 0.95 | 0.98 | V | ||
VCCH_GXBL | Transceiver output buffer power supply | — | 1.710 | 1.8 | 1.890 | V |
14 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.