Intel® Cyclone® 10 GX Device Datasheet

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ID 683828
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Datasheet
Intel® Cyclone® 10 GX Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Cyclone® 10 GX Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Cyclone® 10 GX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Cyclone® 10 GX Devices Transceiver Specifications for Intel® Cyclone® 10 GX Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Cyclone® 10 GX Device Datasheet

Fractional PLL Specifications

Table 30.  Fractional PLL Specifications for Intel® Cyclone® 10 GX Devices
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency — 30 — 800 49 MHz
fINPFD Input clock frequency to the phase frequency detector (PFD) — 30 — 700 MHz
fCASC_INPFD Input clock frequency to the PFD of destination cascade PLL — 30 — 60 MHz
fVCO PLL voltage-controlled oscillator (VCO) operating range — 6 — 12.5 GHz
tEINDUTY Input clock duty cycle — 45 — 55 %
fOUT Output frequency for internal global or regional clock — — — 644 MHz
fDYCONFIGCLK Dynamic configuration clock for reconfig_clk — — — 100 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of pll_powerdown — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
fCLBW PLL closed-loop bandwidth — 0.3 — 4 MHz
tPLL_PSERR Accuracy of PLL phase shift — — — 50 ps
tARESET Minimum pulse width on the pll_powerdown signal — 10 — — ns
tINCCJ 50 51 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.13 UI (p-p)
FREF < 100 MHz — — 650 ps (p-p)
tOUTPJ 52 Period jitter for clock output FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tOUTCCJ 52 Cycle-to-cycle jitter for clock output FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
dKBIT Bit number of Delta Sigma Modulator (DSM) — — 32 — bit
Related Information
49 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
50 A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
51 FREF is fIN/N, specification applies when N = 1.
52 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specification for Intel® Cyclone® 10 GX Devices table.
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