Intel® Cyclone® 10 GX Device Datasheet

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ID 683828
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Datasheet
Intel® Cyclone® 10 GX Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Cyclone® 10 GX Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Cyclone® 10 GX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Cyclone® 10 GX Devices Transceiver Specifications for Intel® Cyclone® 10 GX Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Cyclone® 10 GX Device Datasheet

Document Revision History for the Intel® Cyclone® 10 GX Device Datasheet

Document Version Changes
2022.02.14
  • Updated VCCBAT specifications in the Recommended Operating Conditions for Intel® Cyclone® 10 GX Devices table.
  • Removed table description from the I/O Pin Leakage Current for Intel® Cyclone® 10 GX Devices table.
  • Updated the Differential I/O Standards Specifications for Intel® Cyclone® 10 GX Devices table.
    • Changed I/O standard from RSDS (HIO) to RSDS.
    • Changed I/O standard from Mini-LVDS (HIO) to Mini-LVDS and updated footnote.
  • Removed diagram: DPA Lock Time Specifications with DPA PLL Calibration Enabled
  • Added footnote to Maximum Data Transition in the DPA Lock Time Specifications for Intel® Cyclone® 10 GX Devices table.
  • Updated tCF2CD and tCF2ST0 minimum specifications in the FPP Timing Parameters When the DCLK-to-DATA[] Ratio is 1 for Intel® Cyclone® 10 GX Devices table.
  • Updated the FPP Timing Parameters When the DCLK-to-DATA[] Ratio is >1 for Intel® Cyclone® 10 GX Devices table.
    • Updated tCF2CD and tCF2ST0 minimum specifications.
    • Removed tR and tF specifications.
  • Updated tCF2CD and tCF2ST0 minimum specifications in the PS Timing Parameters for Intel® Cyclone® 10 GX Devices table.
  • Updated the Configuration Bit Stream Sizes for Intel® Cyclone® 10 GX Devices table.
    • Updated table description.
    • Updated Uncompressed Configuration Bit Stream Size and IOCSR Bit Stream Size.
  • Updated Minimum Configuration Time in the Minimum Configuration Time Estimation for Intel® Cyclone® 10 GX Devices table.
2018.06.15
  • Added Intel® Cyclone® 10 GX Devices Overshoot Duration figure and description.
  • Added a link in the OCT Calibration Accuracy Specifications section.
  • Removed Equation for OCT Variation Without Recalibration.
  • Updated the note to CLKUSR in the Initialization Clock Source Option and the Maximum Frequency for Intel® Cyclone® 10 GX Devices table.
  • Updated the I/O Timing section on the I/O timing information generation guidelines.
  • Updated the description and maximum offset values in the IOE Programmable Delay for Intel® Cyclone® 10 GX Devices table.
2018.04.06 Added notes to IOUT specification in the Absolute Maximum Ratings for Intel® Cyclone® 10 GX Devices table.
Date Version Changes
November 2017 2017.11.10
  • Changed the full symbol names for VCCR_GXB and VCCT_GXB, and changed the description for VCCH_GXB in the Transceiver Power Supply Operating Conditions for Intel® Cyclone® 10 GX Devices table.
  • Removed note from the Transceiver Power Supply Operating Conditions section.
  • Added a footnote in the Reference Clock Specifications table.
  • Removed the "Programmable AC Gain at High Gain mode and Data Rate ≤ 12.5 Gbps" parameter from the Receiver Specifications table.
  • Changed the channel span descriptions for the x1 and x6 clock networks in the Transceiver Clock Network Maximum Data Rate Specifications table.
  • Changed the description of the VOD ratio in the Typical Transmitter VOD Settings table.
  • Changed the specifications for CDR PPM deviation limit in the Receiver Specifications table.
  • Updated the description for VCCT_GXB, VCCR_GXB, and VCCH_GXB.
  • Added note to VI in the Recommended Operating Conditions for Intel® Cyclone® 10 GX Devices table.
  • Updated notes to RSDS and Mini-LVDS in the Differential I/O Standards Specifications for Intel® Cyclone® 10 GX Devices table.
  • Updated fVCO specifications in the Fractional PLL Specifications for Intel® Cyclone® 10 GX Devices table.
  • Updated temperature range from "–40 to 125°C" to "–40 to 100°C" in the Internal Temperature Sensing Diode Specifications for Intel® Cyclone® 10 GX Devices table.
  • Updated the description for the Memory Output Clock Jitter Specifications for Intel® Cyclone® 10 GX Devices table.
  • Updated the following IP cores name:
    • Remote Update Intel® FPGA
    • PHYLite for Parallel Interfaces Intel® Cyclone® 10 FPGA
  • Removed automotive-grade information.
  • Removed Preliminary tags.
May 2017 2017.05.08 Initial release.
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