Intel® Cyclone® 10 GX Device Datasheet

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ID 683828
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Datasheet
Intel® Cyclone® 10 GX Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Cyclone® 10 GX Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Cyclone® 10 GX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Cyclone® 10 GX Devices Transceiver Specifications for Intel® Cyclone® 10 GX Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Cyclone® 10 GX Device Datasheet

Memory Block Specifications

To achieve the maximum memory block performance, use a memory block clock that comes through global clock routing from an on-chip PLL and set to 50% output duty cycle. Use the Intel® Quartus® Prime software to report timing for the memory block clocking schemes.

When you use the error detection cyclical redundancy check (CRC) feature, there is no degradation in fMAX.

Table 33.  Memory Block Performance Specifications for Intel® Cyclone® 10 GX Devices
Memory Mode Performance
–E5, –I5 –E6 –I6 Unit
MLAB Single port, all supported widths (×16/×32) 570 490 490 MHz
Simple dual-port, all supported widths (×16/×32) 570 490 490 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 400 330 330 MHz
ROM, all supported width (×16/×32) 570 490 490 MHz
M20K Block Single-port, all supported widths 625 530 510 MHz
Simple dual-port, all supported widths 625 530 510 MHz
Simple dual-port with the read-during-write option set to Old Data, all supported widths 470 410 410 MHz
Simple dual-port with ECC enabled, 512 × 32 410 360 360 MHz
Simple dual-port with ECC and optional pipeline registers enabled, 512 × 32 520 470 470 MHz
True dual port, all supported widths 600 480 480 MHz
ROM, all supported widths 625 530 510 MHz
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