Intel® Cyclone® 10 GX Device Datasheet

Download PDF
ID 683828
Date 2/14/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Datasheet
Intel® Cyclone® 10 GX Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Cyclone® 10 GX Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Switching Characteristics x
Transceiver Performance Specifications Core Performance Specifications Periphery Performance Specifications
Transceiver Performance Specifications x
Transceiver Performance for Intel® Cyclone® 10 GX Devices High-Speed Serial Transceiver-Fabric Interface Performance for Intel® Cyclone® 10 GX Devices Transceiver Specifications for Intel® Cyclone® 10 GX Devices
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Temperature Sensing Diode Specifications x
Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller DLL Range Specifications DQS Logic Block Specifications Memory Output Clock Jitter Specifications OCT Calibration Block Specifications
Configuration Specifications x
POR Specifications JTAG Configuration Timing FPP Configuration Timing AS Configuration Timing DCLK Frequency Specification in the AS Configuration Scheme PS Configuration Timing Initialization Configuration Files Minimum Configuration Time Estimation Remote System Upgrades User Watchdog Internal Circuitry Timing Specifications
FPP Configuration Timing x
DCLK-to-DATA[] Ratio (r) for FPP Configuration FPP Configuration Timing when DCLK-to-DATA[] = 1 FPP Configuration Timing when DCLK-to-DATA[] >1
Intel® Cyclone® 10 GX Device Datasheet

Minimum Configuration Time Estimation

Table 55.  Minimum Configuration Time Estimation for Intel® Cyclone® 10 GX DevicesThe estimated values are based on the uncompressed configuration bit stream sizes in the Configuration Bit Stream Sizes for Intel® Cyclone® 10 GX Devices table.
Variant Product Line Active Serial 85 Fast Passive Parallel 86
Width DCLK (MHz) Minimum Configuration Time (ms) Width DCLK (MHz) Minimum Configuration Time (ms)
Intel® Cyclone® 10 GX GX 085 4 100 229.32 32 100 28.67
GX 105 4 100 229.32 32 100 28.67
GX 150 4 100 229.32 32 100 28.67
GX 220 4 100 229.32 32 100 28.67
Related Information
85 The minimum configuration time is calculated based on DCLK frequency of 100 MHz. Only external CLKUSR may guarantee the frequency accuracy of 100 MHz. If you use internal oscillator of 100 MHz, you may not get the actual frequency of 100 MHz. For the DCLK frequency using internal oscillator, refer to the DCLK Frequency Specification in the AS Configuration Scheme table.
86 Maximum FPGA FPP bandwidth may exceed bandwidth available from some external storage or control logic.
Level Two Title