Visible to Intel only — GUID: nmq1488510813723
Ixiasoft
Single-Ended I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications
Differential SSTL I/O Standards Specifications
Differential HSTL and HSUL I/O Standards Specifications
Differential I/O Standards Specifications
High-Speed I/O Specifications
DPA Lock Time Specifications
LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications
Memory Standards Supported by the Hard Memory Controller
DLL Range Specifications
DQS Logic Block Specifications
Memory Output Clock Jitter Specifications
OCT Calibration Block Specifications
POR Specifications
JTAG Configuration Timing
FPP Configuration Timing
AS Configuration Timing
DCLK Frequency Specification in the AS Configuration Scheme
PS Configuration Timing
Initialization
Configuration Files
Minimum Configuration Time Estimation
Remote System Upgrades
User Watchdog Internal Circuitry Timing Specifications
Visible to Intel only — GUID: nmq1488510813723
Ixiasoft
Recommended Operating Conditions
Symbol | Description | Condition | Minimum 8 | Typical | Maximum 8 | Unit |
---|---|---|---|---|---|---|
VCC | Core voltage power supply | — | 0.87 | 0.9 | 0.93 | V |
VCCP | Periphery circuitry and transceiver fabric interface power supply | — | 0.87 | 0.9 | 0.93 | V |
VCCPGM | Configuration pins power supply | 1.8 V | 1.71 | 1.8 | 1.89 | V |
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.2 V | 1.14 | 1.2 | 1.26 | V | ||
VCCERAM | Embedded memory power supply | 0.9 V | 0.87 | 0.9 | 0.93 | V |
VCCBAT 9 | Battery back-up power supply (For design security volatile key register) | — | 1.14 | — | 1.89 | V |
VCCPT | Power supply for programmable power technology and I/O pre-driver | 1.8 V | 1.71 | 1.8 | 1.89 | V |
VCCIO | I/O buffers power supply | 3.0 V (for 3 V I/O only) | 2.85 | 3.0 | 3.15 | V |
2.5 V (for 3 V I/O only) | 2.375 | 2.5 | 2.625 | V | ||
1.8 V | 1.71 | 1.8 | 1.89 | V | ||
1.5 V | 1.425 | 1.5 | 1.575 | V | ||
1.35 V | 10 | 1.35 | 10 | V | ||
1.25 V | 1.19 | 1.25 | 1.31 | V | ||
1.2 V | 10 | 1.2 | 10 | V | ||
VCCA_PLL | PLL analog voltage regulator power supply | — | 1.71 | 1.8 | 1.89 | V |
VREFP_ADC | Precision voltage reference for voltage sensor | — | 1.2475 | 1.25 | 1.2525 | V |
VI 11 12 | DC input voltage | 3 V I/O | –0.3 | — | 3.3 | V |
LVDS I/O | –0.3 | — | 2.19 | V | ||
VO | Output voltage | — | 0 | — | VCCIO | V |
TJ | Operating junction temperature | Extended | 0 | — | 100 | °C |
Industrial | –40 | — | 100 | °C | ||
tRAMP 13 | Power supply ramp time | Standard POR | 200 µs | — | 100 ms | — |
Fast POR | 200 µs | — | 4 ms | — |
Related Information
8 This value describes the budget for the DC (static) power supply tolerance and does not include the dynamic tolerance requirements. Refer to the PDN tool for the additional budget for the dynamic tolerance requirements.
9 If you do not use the design security feature in Intel® Cyclone® 10 GX devices, connect VCCBAT to a 1.5-V to 1.8-V power supply. Intel® Cyclone® 10 GX power-on reset (POR) circuitry monitors VCCBAT. Intel® Cyclone® 10 GX devices do not exit POR if VCCBAT is not powered up.
10 For minimum and maximum voltage values, refer to the I/O Standard Specifications section.
11 The LVDS I/O values are applicable to all dedicated and dual-function configuration I/Os.
12 This value applies to both input and tri-stated output configuration. Pin voltage should not be externally pulled higher than the maximum value.
13 tramp is the ramp time of each individual power supply, not the ramp time of all combined power supplies.