ID
683809
Date
3/28/2022
Public
Visible to Intel only — GUID: cck1554137521662
Ixiasoft
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe®
2.2. DDR4 as Global Memory for OpenCL Applications
2.3. Host Connection to OpenCL Kernels
2.4. Partial Reconfiguration
2.5. Other Components in the Reference Design
2.6. Intel® Stratix® 10 FPGA System Design
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows
2.9. Addition of Timing Constraints
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™
2.11. Intel® Stratix® 10 FPGA Programming Flow
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities
2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access
2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP
2.1.3. Instantiation of the version_id Component
2.1.4. Board Support Package Software Layer
2.1.5. Direct Memory Access
2.1.6. Message Signaled Interrupt
2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
3.1. Initializing Your Intel® Stratix® 10 Custom Platform
3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™
3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment
3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication
3.6. Branding Your Intel® Stratix® 10 Custom Platform
3.7. Changing the Device Part Number
3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform
3.9. Modifying the Kernel PLL Reference Clock
3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform
3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
Visible to Intel only — GUID: cck1554137521662
Ixiasoft
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
Updated for: |
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Intel® Quartus® Prime Design Suite 19.1 |
The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide describes procedures and design considerations for modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform (s10_ref) into your own Custom Platform for use with the Intel® FPGA Software Development Kit (SDK) for OpenCL™ 1 2 .
1
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission of the Khronos Group™.
2
The Intel® FPGA SDK for OpenCL™ is based on a published Khronos specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.