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2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe®
2.2. DDR4 as Global Memory for OpenCL Applications
2.3. Host Connection to OpenCL Kernels
2.4. Partial Reconfiguration
2.5. Other Components in the Reference Design
2.6. Intel® Stratix® 10 FPGA System Design
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows
2.9. Addition of Timing Constraints
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™
2.11. Intel® Stratix® 10 FPGA Programming Flow
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities
2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access
2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP
2.1.3. Instantiation of the version_id Component
2.1.4. Board Support Package Software Layer
2.1.5. Direct Memory Access
2.1.6. Message Signaled Interrupt
2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
3.1. Initializing Your Intel® Stratix® 10 Custom Platform
3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™
3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment
3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication
3.6. Branding Your Intel® Stratix® 10 Custom Platform
3.7. Changing the Device Part Number
3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform
3.9. Modifying the Kernel PLL Reference Clock
3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform
3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
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2.9. Addition of Timing Constraints
A Custom Platform must apply the correct timing constraints to the Intel® Quartus® Prime project. In the Intel® Stratix® 10 FPGA Development Kit Reference Platform, the top.sdc file contains all timing constraints applicable before IP instantiation in Platform Designer. The top_post.sdc file contains timing constraints applicable after Platform Designer generation is run.
The order of the application of time constraints is based on the order of appearance of the top.sdc and top_post.sdc files in the flat.qsf file. To ensure proper SDC ordering, the opencl_bsp_ip.qsf file is sourced between top.sdc and top_post.sdc files. All IPs are added to opencl_bsp_ip.qsf during aoc compile flow. This ensures that the SDC order is top.sdc followed by SDCs for the IP components and then top_post.sdc in all aoc compiles.
An important constraint in the s10_ref Reference Platform is the multicycle constraint for the kernel reset in the top_post.sdc file. Using global routing saves routing resources and provides more balanced skew. However, the delay across the global route might cause recovery timing issues that limit kernel clock speed. Therefore, it is necessary to include a multicycle path on the global reset signal.
#Make the kernel reset multicycle
#changes made to the multicycle path here need to also be reflected in the
#multicycle value in scripts/adjust_plls_s10.tcl
Set_multicycle_path -to * -setup 15 -from {freeze_wrapper_inst|board_kernel_reset_n_reg}
Set_multicycle_path -to * -hold 14 -from {freeze_wrapper_isnt|board_kernel_reset_reset_n_reg}