Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683809
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture 3. Developing Your Intel® Stratix® 10 Custom Platform 4. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Introduction to Intel® Reference Platform 1.2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform 1.4. Contents of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform
1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform x
1.3.1. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Board Variants
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture x
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® 2.2. DDR4 as Global Memory for OpenCL Applications 2.3. Host Connection to OpenCL Kernels 2.4. Partial Reconfiguration 2.5. Other Components in the Reference Design 2.6. Intel® Stratix® 10 FPGA System Design 2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows 2.9. Addition of Timing Constraints 2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.11. Intel® Stratix® 10 FPGA Programming Flow 2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® x
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access 2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP 2.1.3. Instantiation of the version_id Component 2.1.4. Board Support Package Software Layer 2.1.5. Direct Memory Access 2.1.6. Message Signaled Interrupt 2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
2.1.4. Board Support Package Software Layer x
2.1.4.1. Common Hardware Constants in Software Headers Files 2.1.4.2. PCIe Kernel Driver 2.1.4.3. Host-to-Device MMD Software Implementation
2.1.5. Direct Memory Access x
2.1.5.1. Implementing a DMA Transfer
2.2. DDR4 as Global Memory for OpenCL Applications x
2.2.1. DDR4 IP Instantiation 2.2.2. DDR4 Connection to PCIe Host 2.2.3. DDR4 Connection to the OpenCL Kernel
2.4. Partial Reconfiguration x
2.4.1. Constant Address Bridge (constant_address_bridge)
2.6. Intel® Stratix® 10 FPGA System Design x
2.6.1. Clocks 2.6.2. Resets 2.6.3. Floorplan 2.6.4. Global Routing 2.6.5. Pipelining 2.6.6. DDR4 Calibration
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design x
2.7.1. Supply the Kernel Clock 2.7.2. Guarantee Kernel Clock Timing 2.7.3. Provide a Timing-Closed Post-Fit Netlist
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows x
2.8.1. Compile Flow 2.8.2. Platform Designer System Generation 2.8.3. QAR/QDB File Generation
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ x
2.10.1. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.10.2. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
2.12.1. aocl install 2.12.2. aocl uninstall 2.12.3. aocl program 2.12.4. aocl flash 2.12.5. aocl diagnose 2.12.6. aocl list-devices
3. Developing Your Intel® Stratix® 10 Custom Platform x
3.1. Initializing Your Intel® Stratix® 10 Custom Platform 3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment 3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication 3.6. Branding Your Intel® Stratix® 10 Custom Platform 3.7. Changing the Device Part Number 3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform 3.9. Modifying the Kernel PLL Reference Clock 3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform 3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture
3. Developing Your Intel® Stratix® 10 Custom Platform
4. Document Revision History

3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™

When modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform into your own Custom Platform, ensure that guaranteed timing closure holds true for your Custom Platform. Follow the steps below to ensure your design meets timing, to check your BSP with multiple kernels and to implement top revision compile flow.
  1. Set AOCL_BOARD_PACKAGE_ROOT to point to your custom platform. Use flat.qsf file in INTELFPGAOCLSDKROOT/board/s10_ref reference platform to determine the type of information you must include in the flat.qsf file for your Custom Platform.
  2. Update the <your_custom_platform>/hardware/<board_name>/board_spec.xml file. Ensure that there is at least one global memory interface, and all global memory interfaces correspond to the exported interfaces from the board.qsys Platform Designer system file.
  3. After all your hardware design changes are finalized, compile flat revision with several seeds of the INTELFPGAOCLSDKROOT/board/custom_platform_toolkit/tests/boardtest/boardtest.cl kernel until you generate a design that closes timing cleanly.
    To specify the seed number during compile, include the -seed=<N> option in your aoc command. Use -bsp-flow=flat option in your aoc command for flat compile. 
    aoc -bsp-flow=flat boardtest.cl -o=bin/boardtest.aocx
  4. Based on the output of your flat revision compiles, establish the floorplan of your design in base revision. Add Logic Lock regions in base.qsf only. base.qsf and top.qsf files automatically inherit all the settings in the flat.qsf file.
    Important: Consider all design criteria outlined in the Intel® Stratix® 10 FPGA System Design section in this guide. Compile base revision with several seeds of the INTELFPGAOCLSDKROOT/board/ custom_platform_toolkit/tests/boardtest/boardtest.cl kernel until you generate a design that closes timing cleanly. This flow is used to create the timing closed base database for the static region which is needed for guaranteed timing support. Use -bsp-flow=base option in your aoc command for base compile. 
    aoc -bsp-flow=base boardtest.cl -o=bin/boardtest.aocx
    Attention: In a typical development of a custom platform, designers generally validate the functionality of boardtest using the flat flow before starting to add guaranteed timing functionality to their BSP.
  5. From the compiled output directory for base revision compile, copy base.qar file into your Custom Platform hardware directory to replace old base.qar with new base.qar containing post-fit netlist for your reference platform.
  6. Make sure AOCL_BOARD_PACKAGE_ROOT is set to your reference platform with new base.qar and compile top revision, that is, default compilation flow. Confirm that you can use the .aocx file to reprogram the FPGA by invoking the aocl program acl0 boardtest.aocx command.
  7. Using the default compilation flow, test your base.qar file across several OpenCL design examples and confirm that the following criteria are satisfied:
    • All compilations close timing.
    • The OpenCL design examples achieve satisfactory fmax (Check the acl quartus_report.txt for achieved fmax).
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