Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683809
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture 3. Developing Your Intel® Stratix® 10 Custom Platform 4. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Introduction to Intel® Reference Platform 1.2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform 1.4. Contents of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform
1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform x
1.3.1. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Board Variants
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture x
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® 2.2. DDR4 as Global Memory for OpenCL Applications 2.3. Host Connection to OpenCL Kernels 2.4. Partial Reconfiguration 2.5. Other Components in the Reference Design 2.6. Intel® Stratix® 10 FPGA System Design 2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows 2.9. Addition of Timing Constraints 2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.11. Intel® Stratix® 10 FPGA Programming Flow 2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® x
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access 2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP 2.1.3. Instantiation of the version_id Component 2.1.4. Board Support Package Software Layer 2.1.5. Direct Memory Access 2.1.6. Message Signaled Interrupt 2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
2.1.4. Board Support Package Software Layer x
2.1.4.1. Common Hardware Constants in Software Headers Files 2.1.4.2. PCIe Kernel Driver 2.1.4.3. Host-to-Device MMD Software Implementation
2.1.5. Direct Memory Access x
2.1.5.1. Implementing a DMA Transfer
2.2. DDR4 as Global Memory for OpenCL Applications x
2.2.1. DDR4 IP Instantiation 2.2.2. DDR4 Connection to PCIe Host 2.2.3. DDR4 Connection to the OpenCL Kernel
2.4. Partial Reconfiguration x
2.4.1. Constant Address Bridge (constant_address_bridge)
2.6. Intel® Stratix® 10 FPGA System Design x
2.6.1. Clocks 2.6.2. Resets 2.6.3. Floorplan 2.6.4. Global Routing 2.6.5. Pipelining 2.6.6. DDR4 Calibration
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design x
2.7.1. Supply the Kernel Clock 2.7.2. Guarantee Kernel Clock Timing 2.7.3. Provide a Timing-Closed Post-Fit Netlist
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows x
2.8.1. Compile Flow 2.8.2. Platform Designer System Generation 2.8.3. QAR/QDB File Generation
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ x
2.10.1. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.10.2. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
2.12.1. aocl install 2.12.2. aocl uninstall 2.12.3. aocl program 2.12.4. aocl flash 2.12.5. aocl diagnose 2.12.6. aocl list-devices
3. Developing Your Intel® Stratix® 10 Custom Platform x
3.1. Initializing Your Intel® Stratix® 10 Custom Platform 3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment 3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication 3.6. Branding Your Intel® Stratix® 10 Custom Platform 3.7. Changing the Device Part Number 3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform 3.9. Modifying the Kernel PLL Reference Clock 3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform 3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture
3. Developing Your Intel® Stratix® 10 Custom Platform
4. Document Revision History

1.4. Contents of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform

Familiarize yourself with directories and files within the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform ( INTELFPGAOCLSDKROOT/board/s10_ref because they are referenced throughout this document.
Table 2.  Highlights of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Directory
Windows File or Folder Linux File or Directory Description
board_env.xml board_env.xml eXtensible Markup Language (XML) file that describes the Reference Platform to the Intel® FPGA SDK for OpenCL™ .
bringup bringup Contains initialization binaries and Intel® Stratix® 10 Development Kit Initialization guide (S10_DevKit_Initialization).
hardware hardware Contains the Intel® Quartus® Prime project templates for the s10gx board variant.

See Contents of the s10gx Directory for a list of files in this directory.

windows64 linux64 Contains the MMD library, kernel mode driver, and executable files of the SDK utilities (that is, install, uninstall, flash, program, diagnose) for your 64-bit operating system.
source source

For Windows, the source folder contains source codes for the MMD library and SDK utilities. The MMD library and the SDK utilities are in the windows64 folder.

For Linux, the source directory contains source codes for the MMD library and SDK utilities. The MMD library and the SDK utilities are in the linux64 directory.

scripts scripts Contains the find_jtag_cable.tcl script that is useful in identifying the cable and index number required for FPGA programming.
Table 3.  Contents of the s10gx DirectoryThe following table lists the files in the INTELFPGAOCLSDKROOT/board/s10_ref/hardware/s10gx directory, where INTELFPGAOCLSDKROOT points to the location of the SDK installation.
File Description
mem.qsys Platform Designer system that, together with the .ip files in the ip/mem/ sub-directory, implements the mem component. It can be recognized as the memory subsystem instantiated in the board.qsys. It contains EMIF hard IP, AVMM S10 CCBs (Clock Crossing Bridge), ACL Uniphy Status and ACL SW Reset (Calibration) components.
board.qsys Platform Designer system that implements the board interfaces (that is, the static region) of the OpenCL hardware system.
device.tcl Tcl file that is included in all revisions and contains all device-specific information (for example, device family, ordering part number (OPN), voltage settings, pin assignments and so on). It is sourced in other QSF files, such as opencl_bsp_ip.qsf and flat.qsf.
opencl_bsp_ip.qsf Intel® Quartus® Prime Settings File that collects all the required .ip files in a unique location.

During flat and base revision compilations, the board.qsys and mem.qsys related IP files are added to the opencl_bsp_ip.qsf file.

flat.qsf Intel® Quartus® Prime Settings File for the flat project revision. This file includes all common settings, such as VID and global signal settings, that are used in other revisions of the project (that is, base and top). The base.qsf and top.qsf files include, by reference, all settings in the flat.qsf file.

The Intel® Quartus® Prime software compiles the flat revision with minimal constraints. The flat revision compilation does not generate a base.qar file that you can use for future import compilations and does not implement the guaranteed timing flow. It is used to make edits and check functionality of the design.

base.qsf Intel® Quartus® Prime Settings File for the base project revision. This file includes, by reference, all the settings in the flat.qsf file.

The Intel® Quartus® Prime Pro Edition software compiles this base project revision from source code unlike the top compile that uses the base.qar output.

top.qsf Intel® Quartus® Prime Settings File for the SDK-user compilation flow (import compilation flow).
top.v Top-level Verilog Design File for the OpenCL hardware system.
top.sdc Synopsys Design Constraints File that contains board-specific timing constraints.
top_post.sdc Platform Designer and Intel® FPGA SDK for OpenCL™ IP-specific timing constraints.
ip/mem/<file_name> Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the mem component.

Along with mem.qsys, files in this directory are required for flat and base revision compiles. These are added to the flow by pre_flow_pr.tcl.

ip/board/<file_name> Directory containing the .ip files that the Intel® Quartus® Prime Pro Edition software needs to parameterize the board instance.

Along with board.qsys, files in this directory are required for flat and base revision compiles. These are added to the flow by pre_flow_pr.tcl

ip/freeze_wrapper.v Verilog Design File that implements the freeze logic. Freeze logic allows user to construct the building blocks for a design that is suitable for Partial Reconfiguration.
ip/pr_region.v Verilog Design File that contains the Partial Reconfiguration (PR) region logic.
ip/temperature/<file_name> A wrapper to the actual temperature IP that has an Avalon streaming interface. The wrapper sets the necessary default values and converts the interface to an AVMM interface so that it can be used by other IPs.
ip/irq_controller/<file_name> IP that receives interrupts from the OpenCL kernel system and sends message signaled interrupts (MSI) to the host.

Refer to the Message Signaled Interrupts section for more information.

compile_script.tcl Tcl script for SDK compilation flows.
scripts/create_fpga_bin_pr.tcl Tcl script that generates the ELF binary file, fpga.bin from .sof, .rbf, and pr_base.id files. The fpga.bin file contains all files necessary for configuring the FPGA.
scripts/qar_ip_files.tcl Tcl script that packages up base.qdb, pr_base.id, base.sdc, board and mem Platform Designer system generation output during base revision compile.
scripts/helpers.tcl Tcl script with helper functions used by qar_ip_files.tcl.
scripts/post_flow_pr.tcl Tcl script that runs after every Intel® Quartus® Prime Pro Edition software compilation. It facilitates the guaranteed timing flow by setting the kernel clock PLL, generating a small report in the acl_quartus_report.txt file, and rerunning STA with the modified kernel clock settings.
scripts/pre_flow_pr.tcl Tcl script that executes before the invocation of the Intel® Quartus® Prime software compilation. Running the script generates the Platform Designer HDL for board.qsys.
scripts/get_static_region_kernel_fmax.tcl Tcl script to generate reports for kernel clk worst paths in static region.
Note: The region where pre-compiled BSP hardware design is placed is called Static region.
scripts/regenerate_cache.tcl Helper scripts for bak flow.
scripts/base_write_sdc.tcl Tcl script to save the SDC from a base revision compile.
scripts/create_acds_ver_hex.tcl Tcl script to burn Intel® Quartus® Prime software version to ROM during compile.
adjust_plls.tcl Tcl script that is not part of the scripts directory, but it is an important script to know about. This PLL adjustment script for the kernel clock PLL guarantees timing closure on the kernel clock by setting it to the maximum allowed frequency.
base.qar Intel® Quartus® Prime Archive File that contains base.qdb, pr_base.id, base.sdc, board and mem Platform Designer generation output from base revision compile. This Intel® Quartus® Prime Archive file is generated by the scripts/post_flow_pr.tcl file during base revision compile and is used during top revision compilation.
base.qdb
Intel® Quartus® Prime Database Export File that contains the precompiled netlist of the static regions of the design.
pr_base.id
Text file containing a unique number for a given base compilation that the runtime uses to determine whether it is safe to use PR programming.
base.sdc
Synopsis Design Constraint file for base revision that is generated by base_write_sdc.tcl during base revision compile.
top.qpf Intel® Quartus® Prime Project File for the OpenCL hardware system.
quartus.ini Contains any special Intel® Quartus® Prime software options that you need to compile OpenCL kernels for the s10_ref Reference Platform.
iface.ipx Specifies the relative path of directories to search for IP cores. In general, .ipx (that is, IP Index Files) files facilitate faster searches. iface.ipx is a top-level .ipx file that references hw_iface.iipx and sw_iface.iipx (intermediate-ipx) files.
hw_iface.ipx Intermediate IP Index file. It is an XML file that consists of <component> elements with attributes to define some of the BSP components.
sw_iface.ipx Intermediate IP Index file.
board_spec.xml XML file that provides the definition of the board hardware interfaces to the SDK.
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