| 2019.04.01 |
19.1 |
- Intel Stratix 10 GX FPGA Development Kit Reference Platform Design Architecture and Developing Your Intel Stratix 10 Custom Platform chapters interchanged.
- Few topics were rearranged in this guide.
- Changed all occurrences of s10gx_ea_htile to s10gx.
- Added the following new topics:
- Removed following topics:
- Intel® Quartus® Prime Compilation Flow and Scripts
- Intel® Quartus® Prime Compilation Flow for Board Developers
- Intel® Quartus® Prime Compilation Flow for Custom Platform Users
- Intel® Arria® 10 FPGA Development Kit Reference Platform Scripts and its content was merged with Contents of the Intel Stratix 10 GX FPGA Development Kit Reference Platform.
- Guaranteeing Timing Closure in the Custom Platform
- Generating the base.qar Post-Fit Netlist for Your Custom Platform
- Define the Contents of the fpga.bin File for the Intel Stratix 10 GX FPGA Development Kit Reference Platform
- In Intel Stratix 10 GX FPGA Development Kit Reference Platform: Prerequisites, following changes were made:
- altera_s10pciedk changed to s10_ref
- Removed the statement about testing interfaces together in the same design.
- In Features of the Intel Stratix 10 GX FPGA Development Kit Reference Platform, following changes were made:
- For OpenCL Host, PCIe Gen2x8 hard IP core updated to PCIe Gen3x8 hard IP core.
- Updated the OpenCL Global Memory description.
- Updated Hardware Features of the Intel Stratix 10 GX FPGA Development Kit image to show the HiLo Connector.
- In Intel Stratix 10 GX FPGA Development Kit Reference Platform Board Variants, removed reference to RevA silicon and -3 grade speed.
- In Contents of the Intel Stratix 10 GX FPGA Development Kit Reference Platform, following changes were made:
- In Highlights of the Intel Stratix 10 GX FPGA Development Kit Reference Platform Directory table, bringup and scripts directories were added along with their descriptions, and source_windows64 was changed to source.
- In Contents of the s10gx Directory table:
- Rearranged the file list.
- Removed max5_116.pof, top_synth.qsf, root_partition.qdb and scripts/kernel_system_update.tcl.
- Added ip/pr_region.v, ip/temperature/<file_name>, scripts/regenerate_cache.tcl, scripts/base_write_sdc.tcl, scripts/create_acds_ver_hex.tcl, adjust_plls_s10.tcl, hw_iface.ipx, sw_iface.ipx, and board_spec.xml.
- Updated the descriptions of mem.qsys, scripts/create_fpga_bin_pr.tcl, scripts/post_flow_pr.tcl, opencl_bsp_ip.qsf, flat.qsf, device.tcl, ip/mem/<file_name> , scripts/pre_flow_pr.tcl, base.qar and base.qsf descriptions updated.
- Changed acl_ddr4_s10.qsys to mem.qsys
- Changed ip/acl_ddr4_s10/ to ip/mem/
- Changed import_compile.tcl to compile_script
- Changed scripts/adjust_plls_s10.tcl to scripts/get_static_region_kernel_fmax.tcl and updated its description.
- Updated the description of base.qar scripts/qar_ip_files.tcl.
- In Intel Stratix 10 GX FPGA Development Kit Reference Platform Design Architecture, added an image to illustrate the system design of s10_ref platform hardware project.
- Updated the description in Host-to- Intel Stratix 10 FPGA Communication over PCIe.
- In Highlights of Intel Stratix 10 PCIe Hard IP Parameter Settings table, following changes were made:
- For Application interface type parameter, mentioned about Enable Avalon-MM DMA.
- For Hard IP mode, changed to Gen3x8 and 250 MHz, and Gen3 lane rate. Removed the note.
- Removed Rx Buffer credit allocation.
- For Instantiate Internal Descriptor Controller, removed the statement discussing ip/host_channel sub-directory.
- In Base Address Registers (BARs), changed 256 KBytes - 18 bits to 18 bits (256 KBytes).
- In Device Identification Registers for Intel Stratix 10 PCIe Hard IP, following changes were made:
- vendor_id_hwtcl changed to Vendor ID
- device_id_hwtcl changed to Device ID
- — to changed Revision ID
- — to changed Class Code
- subsystem_vendor_id_hwtcl changed to Subsystem Vendor ID
- subsystem_device_id_hwtcl changed to Subsystem Device ID
- For Device ID, changed the Device ID value to 0x5170
- Changed the Revision ID path for Windows.
- In Instantiation of the version_id Component, updated the version ID of s10_ref reference platform.
- In Common Hardware Constants in Software Headers Files, following changes were made:
- Modified the topic title.
- Added an important note about matching MMD offsets in the address map.
- For hw_pcie_constants.h header file, made minor update to the description.
- Added an image depicting Address Map and a snapshot of hw_pcie_constants.h file.
- In PCIe Kernel Driver, following changes were made:
- Modified the topic title.
- Changed path_to_sl0pciedk to path_to_sl0_ref
- Removed Jungo driver related information.
- In Host-to-Device MMD Software Implementation, replaced <your_custom_platform> with INTELFPGAOCLSDKROOT/board/s10_ref and removed references to <your_custom_platform>.
- In Implementing a DMA Transfer, aclpci_dma changed to aclpci_dma.c and removed Jungo driver related information.
- In Message Signaled Interrupt, changed s10gx_ea_htile to s10gx and pcie_irq_0 to pcie_irq.
- In Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature, following changes were made:
- Modified the topic title.
- Description was updated.
- cade_id was changed to board_cade_id_0
- board_in_system_sources_probes_cade_id changed to board_in_system_sources_probes_0
- In DDR4 as Global Memory for OpenCL Applications, following changes were made:
- acl_ddr4_s10.qsys changed to mem.qsys
- Updated the description by removing outdated statements.
- In DDR4 IP Instantiation, updated the DDR4 SDRAM Controller IP Configuration Highlights and added an important note about limitations.
- In DDR4 Connection to PCIe Host, following changes were made:
- Mentioned about memory_band_divider_ddr4a component in board.qsys and added detailed description about it.
- Removed paragraph about Avalon master interfaces.
- Added two more bullet items to the Important note about designing multi-bank OpenCL BSP and Address Span Extender.
- In DDR4 Connection to the OpenCL Kernel, added information about hyper-optimized bridges and important note about the same.
- In Host Connection to OpenCL Kernels, updated the OpenCL Kernel Interface component name and mentioned about pcie_irq.
- In Clocks, updated the PCIe clock and DDR4 clock values, and added a note about kernel_clk_gen.
- In Floorplan, following changes were made:
- Changed all occurrences of Logic Lock Plus to Logic Lock.
- Updated step 1 about compiling the design.
- Floorplan image updated.
- Updated most parts of the description.
- Added an image to depict the Logic Lock regions in base.qsf file.
- In Pipelining, changed pipe_stage_ddr4a_dimm_* to pipe_stage and pipe_stage_ddr4a_dimm to kernel_ddra_bridge
- In DDR4 Calibration, added information about two components in the mem.qsys.
- Made minor update to the description in Guaranteed Timing Closure of the Intel Stratix 10 GX FPGA Development Kit Reference Platform Design.
- In Supply the Kernel Clock, changed pll_refclk to kernel_pll_refclk and value of KERNEL_TARGET_CLOCK_RATE to 500.
- In Guarantee Kernel Clock Timing, changed import_compile.tcl to compile_script.tcl and post_flow.tcl to post_flow_pr.tcl
- In Provide a Timing-Closed Post-Fit Netlist, following changes were made:
- Updated the image of Structure of the Hierarchy on the Intel® Stratix® 10 device.
- Changed top_synth.qsf to opencl_bsp_ip.qsf
- Changed root_partition.qdb to base.qdb
- In Platform Designer System Generation, following changes were made:
- Removed the references to kernel_system.qsys and custom platform directory path.
- Updated the description to include a reference to kernel subsystems and compilation directory.
- Replaced base and import with flat and base revision compilations.
- In QAR/QDB File Generation, following changes were made:
- Replaced .tcl with qar_ip_files.tcl.
- Replaced export_design with qar_ip_files proc
- Included base.sdc file.
- Replaced root_partition.qdb with base.qdb
- Added the last statement of the paragraph.
- In Addition of Timing Constraints, added code snippets and included information about SDC ordering.
- In Connection of the Intel Reference Platform to the Intel FPGA SDK for OpenCL, modified the title and slightly updated the description.
- In Describe the Intel Stratix 10 GX FPGA Development Kit Reference Platform to the Intel FPGA SDK for OpenCL, removed the paragraph discussing Windows dynamic link libraries (DLLs).
- In Describe the Intel Stratix 10 GX FPGA Development Kit Reference Platform Hardware to the Intel FPGA SDK for OpenCL, following changes were made:
- Fitter report updated.
- Changed freeze wrapper inst|kernel_system_inst to freeze wrapper inst|pr_region_inst.
- Updated the used_resources values to match the fitter report.
- Replaced memorg with acl_bsp_memorg_host0x018.
- Replaced memory_bank_divider with memory_bank_divider_ddr4a
- In Intel Stratix 10 FPGA Programming Flow, rewrote bullet 1 statement and added a note about bring-up directory.
- In aocl install and aocl uninstall, removed Jungo driver related information and replaced WinDriver with SSG driver.
- In aocl flash, updated the part number in the image.
- In Initializing Your Intel Stratix 10 Custom Platform, in step 1, replaced drop directory with the actual path and last step and mentioned about AOCL_BOARD_PACKAGE_ROOT.
- In Modifying the Intel Stratix 10 GX FPGA Development Kit Reference Platform Design, modified the last step and removed top_synth.qsf and added more information about SDC ordering.
- In Integrating Your Intel Stratix 10 Custom Platform with the Intel FPGA SDK for OpenCL, all steps were rewritten completely.
- In Setting up the Intel Stratix 10 Custom Platform Software Development Environment, I made the following changes in MMD Layer for Windows instructions:
- Added a new step 3 for Microsoft Visual Studio.
- In step 6, changed gmake and gmake clean to make and make clean.
- Removed Jungo driver related information.
- In Establishing Intel Stratix 10 Custom Platform Host Communication, improved step1 information and added a new step about setting up AOCL_BOARD_PACKAGE_ROOT variable. Mentioned about MMD library in step 6.
- In Branding Your Intel Stratix 10 Custom Platform, replaced source_windows64 with source and modified the step 7.
- In Changing the Device Part Number, following changes were made:
- Updated the device part number.
- Added the flat.qsf to the list.
- Changed top_synth.qsf to opencl_bsp_ip.qsf
- Changed acl_ddr4_s10.qsys to mem.qsys
- In Modifying the Kernel PLL Reference Clock, in step 2, changed "kernel_pll_refclk" to "config_clk in top.sdc" and added more information to optional step 3.
- In Integrating an OpenCL Kernel in Your Intel Stratix 10 Custom Platform, updated step 5 and in step 6, changed Makefile to Makefile.linux and updated its file path. In step 7, added additional information and step 8 was newly added.
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