Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.1.3. Instantiation of the version_id Component

Intel® specifies an additional version ID IP and uses it to verify the address map of the system. The host verifies the version ID of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform when instantiating the version_id component that connects to the PCIe® Avalon® host.

The version ID for the s10_ref Reference Platform is 0xA0C7C1E5 (decimal from signed two's compliment is 1597521435).

Before communicating with any part of the FPGA system, the host first reads from this version_id register to confirm the following:

  • The PCIe can access the FPGA fabric successfully
  • The address map matches the map in the MMD software

Update the VERSION_ID parameter in the version_id component to a new value with every agent addition or removal from the PCIe BAR 4 bus, or whenever the address map changes.