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2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe®
2.2. DDR4 as Global Memory for OpenCL Applications
2.3. Host Connection to OpenCL Kernels
2.4. Partial Reconfiguration
2.5. Other Components in the Reference Design
2.6. Intel® Stratix® 10 FPGA System Design
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows
2.9. Addition of Timing Constraints
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™
2.11. Intel® Stratix® 10 FPGA Programming Flow
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities
2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access
2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP
2.1.3. Instantiation of the version_id Component
2.1.4. Board Support Package Software Layer
2.1.5. Direct Memory Access
2.1.6. Message Signaled Interrupt
2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
3.1. Initializing Your Intel® Stratix® 10 Custom Platform
3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design
3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™
3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment
3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication
3.6. Branding Your Intel® Stratix® 10 Custom Platform
3.7. Changing the Device Part Number
3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform
3.9. Modifying the Kernel PLL Reference Clock
3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform
3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
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3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication
After modifying and rebranding the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to your own Custom Platform, use the tools and utilities in your Custom Platform to establish communication between your FPGA accelerator board and your host application.
- Program your FPGA device with the <your_custom_platform>/hardware/<board_name>/base.sof file and then restart your system.
The base.sof file is generated during base revision compile when integrating your Custom Platform with the Intel® FPGA SDK for OpenCL™ . Refer to the Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ section for more information.
- Confirm that your operating system recognizes a PCIe* device with your vendor and device IDs.
- For Windows, open the Device Manager and verify that the correct device and IDs appear in the listed information.
- For Linux, invoke the lspci command and verify that the correct device and IDs appear in the listed information.
- Set the environment variable AOCL_BOARD_PACKAGE_ROOT to point to your custom platform.
- Run the aocl install <path_to_customplatform> utility command to install the kernel driver on your machine.
- For Windows, set the PATH environment variable. For Linux, set the LD_LIBRARY_PATH environment variable.
For more information about the settings for PATH and LD_LIBRARY_PATH, refer to Setting the Intel® FPGA SDK for OpenCL™ User Environment Variables in the Intel® FPGA SDK for OpenCL™ Getting Started Guide.
- Modify the version_id_test function in your <your_custom_platform>/source/host/mmd/acl_pcie_device.cpp MMD source code file to exit after reading from the version ID register. Rebuild the MMD software.
- Run the aocl diagnose utility command and confirm that the version ID register reads back the ID successfully. You may set the environment variables ACL_HAL_DEBUG and ACL_PCIE_DEBUG to a value of 1 to visualize the result of the diagnostic test on your terminal.