Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

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ID 683809
Date 3/28/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide 2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture 3. Developing Your Intel® Stratix® 10 Custom Platform 4. Document Revision History
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide x
1.1. Introduction to Intel® Reference Platform 1.2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform: Prerequisites 1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform 1.4. Contents of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform
1.3. Features of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform x
1.3.1. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Board Variants
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture x
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® 2.2. DDR4 as Global Memory for OpenCL Applications 2.3. Host Connection to OpenCL Kernels 2.4. Partial Reconfiguration 2.5. Other Components in the Reference Design 2.6. Intel® Stratix® 10 FPGA System Design 2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows 2.9. Addition of Timing Constraints 2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.11. Intel® Stratix® 10 FPGA Programming Flow 2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities 2.13. Considerations in Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Implementation
2.1. Host-to- Intel® Stratix® 10 FPGA Communication over PCIe® x
2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access 2.1.2. Device Identification Registers for Intel® Stratix® 10 PCIe Hard IP 2.1.3. Instantiation of the version_id Component 2.1.4. Board Support Package Software Layer 2.1.5. Direct Memory Access 2.1.6. Message Signaled Interrupt 2.1.7. Instantiation of board_cade_id_0 Component – JTAG Cable Autodetect Feature
2.1.4. Board Support Package Software Layer x
2.1.4.1. Common Hardware Constants in Software Headers Files 2.1.4.2. PCIe Kernel Driver 2.1.4.3. Host-to-Device MMD Software Implementation
2.1.5. Direct Memory Access x
2.1.5.1. Implementing a DMA Transfer
2.2. DDR4 as Global Memory for OpenCL Applications x
2.2.1. DDR4 IP Instantiation 2.2.2. DDR4 Connection to PCIe Host 2.2.3. DDR4 Connection to the OpenCL Kernel
2.4. Partial Reconfiguration x
2.4.1. Constant Address Bridge (constant_address_bridge)
2.6. Intel® Stratix® 10 FPGA System Design x
2.6.1. Clocks 2.6.2. Resets 2.6.3. Floorplan 2.6.4. Global Routing 2.6.5. Pipelining 2.6.6. DDR4 Calibration
2.7. Guaranteed Timing Closure of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design x
2.7.1. Supply the Kernel Clock 2.7.2. Guarantee Kernel Clock Timing 2.7.3. Provide a Timing-Closed Post-Fit Netlist
2.8. Intel® FPGA SDK for OpenCL™ Compilation Flows x
2.8.1. Compile Flow 2.8.2. Platform Designer System Generation 2.8.3. QAR/QDB File Generation
2.10. Connection of the Intel® Reference Platform to the Intel® FPGA SDK for OpenCL™ x
2.10.1. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform to the Intel® FPGA SDK for OpenCL™ 2.10.2. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™ Device Global Memory Interfaces
2.12. Implementation of Intel® FPGA SDK for OpenCL™ Utilities x
2.12.1. aocl install 2.12.2. aocl uninstall 2.12.3. aocl program 2.12.4. aocl flash 2.12.5. aocl diagnose 2.12.6. aocl list-devices
3. Developing Your Intel® Stratix® 10 Custom Platform x
3.1. Initializing Your Intel® Stratix® 10 Custom Platform 3.2. Modifying the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design 3.3. Integrating Your Intel® Stratix® 10 Custom Platform with the Intel® FPGA SDK for OpenCL™ 3.4. Setting up the Intel® Stratix® 10 Custom Platform Software Development Environment 3.5. Establishing Intel® Stratix® 10 Custom Platform Host Communication 3.6. Branding Your Intel® Stratix® 10 Custom Platform 3.7. Changing the Device Part Number 3.8. Connecting the Memory in the Intel® Stratix® 10 Custom Platform 3.9. Modifying the Kernel PLL Reference Clock 3.10. Integrating an OpenCL Kernel in Your Intel® Stratix® 10 Custom Platform 3.11. Troubleshooting Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Issues
1. Intel® FPGA SDK for OpenCL™ Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide
2. Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Design Architecture
3. Developing Your Intel® Stratix® 10 Custom Platform
4. Document Revision History

2.10.2. Describe the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Hardware to the Intel® FPGA SDK for OpenCL™

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform includes an INTELFPGAOCLSDKROOT/board/s10_ref/hardware/s10gx/board_spec.xml file that describes the hardware to the Intel® FPGA SDK for OpenCL™ .

Device

The device section contains the name of the device model file available in the INTELFPGAOCLSDKROOT/share/models/dm directory of the SDK and in the board spec.xml file. The used_resources element accounts for all logic outside of the kernel partition. The value of used_resources for alms equals the difference between the total number of adaptive logic modules (ALMs) used in final placement and the total number of ALMs available to the kernel partition. You can derive this value from the Partition Statistic section of the Fitter report after a compilation. Consider the following ALM categories within an example Fitter report:

Figure 13. Fitter Partition Statistics

The value of used_resources equals the total number of ALMs in l minus the total number of ALMs in freeze wrapper inst|pr_region_inst. In the example above, used_resources = 80273 - 25596 = 54677 ALMs.

You can derive used_resources for rams and dsps in the same way using M20Ks and DSP blocks, respectively. The used_resources value for ffs is four times the used_resources value for alms because there are two primary and two secondary logic registers per ALM.

Note: The Fitter Partition Statistics section can be observed in the Fitter report generated during base or top compiles only.

Global Memory

In the board_spec.xml file, there is one global_mem section for DDR memory. Assign the string DDR to the name attribute of the global_mem element. The board instance in Platform Designer provides all of these interfaces. Therefore, the string board is specified in the name attribute of all the interface elements within global_mem.

  • DDR

    Because DDR memory serves as the default memory for the board that the s10_ref Reference Platform targets, its address attribute begins at zero. Its config_addr is 0x018 to match the acl_bsp_memorg_host0x018 conduit used to connect to the corresponding OpenCL Memory Bank Divider for DDR.

    Attention: The width and burst sizes must match the parameters in the OpenCL Memory Bank Divider for DDR (memory_bank_divider_ddr4a).

Interfaces

The interfaces section describes kernel clocks, reset, CRA, and snoop interfaces. The OpenCL Memory Bank Divider for the default memory (in this case, memory_bank_divider_ddr4a) exports the snoop interface described in the interfaces section. The width of the snoop interface should match the width of the corresponding streaming interface.

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