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1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
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3.4. LVDS Transmitter FPGA Design Implementation
Intel® MAX® 10 devices use a soft SERDES architecture to support high-speed I/O interfaces. The Intel® Quartus® Prime software creates the SERDES circuits in the core fabric by using the Soft LVDS IP core. To improve the timing performance and support the SERDES, Intel® MAX® 10 devices use the I/O registers and LE registers in the core fabric.