Intel® MAX® 10 High-Speed LVDS I/O User Guide

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ID 683760
Date 11/01/2021
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Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 High-Speed LVDS I/O Overview 2. Intel® MAX® 10 High-Speed LVDS Architecture and Features 3. Intel® MAX® 10 LVDS Transmitter Design 4. Intel® MAX® 10 LVDS Receiver Design 5. Intel® MAX® 10 LVDS Transmitter and Receiver Design 6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations 7. Soft LVDS IP Core References 8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives 9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
1. Intel® MAX® 10 High-Speed LVDS I/O Overview x
1.1. Soft LVDS Implementation Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features x
2.1. Intel® MAX® 10 LVDS Channels Support 2.2. Intel® MAX® 10 LVDS SERDES I/O Standards Support 2.3. Intel® MAX® 10 High-Speed LVDS Circuitry 2.4. Intel® MAX® 10 High-Speed LVDS I/O Location 2.5. Differential I/O Pins in Low Speed Region
3. Intel® MAX® 10 LVDS Transmitter Design x
3.1. High-Speed I/O Transmitter Circuitry 3.2. LVDS Transmitter Programmable I/O Features 3.3. LVDS Transmitter I/O Termination Schemes 3.4. LVDS Transmitter FPGA Design Implementation 3.5. LVDS Transmitter Debug and Troubleshooting
3.2. LVDS Transmitter Programmable I/O Features x
3.2.1. Programmable Pre-Emphasis 3.2.2. Programmable Differential Output Voltage
3.3. LVDS Transmitter I/O Termination Schemes x
3.3.1. Emulated LVDS External Termination 3.3.2. Sub-LVDS Transmitter External Termination 3.3.3. SLVS Transmitter External Termination 3.3.4. Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
3.4. LVDS Transmitter FPGA Design Implementation x
3.4.1. Soft LVDS IP Core in Transmitter Mode 3.4.2. High-Speed I/O Timing Budget 3.4.3. Guidelines: LVDS Transmitter Channels Placement 3.4.4. Guidelines: LVDS Channels PLL Placement 3.4.5. Guidelines: LVDS Transmitter Logic Placement 3.4.6. Guidelines: Enable LVDS Pre-Emphasis for E144 Package
3.4.1. Soft LVDS IP Core in Transmitter Mode x
3.4.1.1. PLL Source Selection for Soft LVDS IP Core 3.4.1.2. Guidelines: LVDS TX Interface Using External PLL 3.4.1.3. Initializing the Soft LVDS IP Core
3.4.1.1. PLL Source Selection for Soft LVDS IP Core x
3.4.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 3.4.1.1.2. Instantiate Soft LVDS IP Core with External PLL
3.4.1.2. Guidelines: LVDS TX Interface Using External PLL x
3.4.1.2.1. ALTPLL Signal Interface with Soft LVDS Transmitter 3.4.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Transmitter
3.4.2. High-Speed I/O Timing Budget x
3.4.2.1. Transmitter Channel-to-Channel Skew
3.5. LVDS Transmitter Debug and Troubleshooting x
3.5.1. Perform RTL Simulation Before Hardware Debug 3.5.2. Geometry-Based and Physics-Based I/O Rules
4. Intel® MAX® 10 LVDS Receiver Design x
4.1. High-Speed I/O Receiver Circuitry 4.2. LVDS Receiver I/O Termination Schemes 4.3. LVDS Receiver FPGA Design Implementation 4.4. LVDS Receiver Debug and Troubleshooting
4.1. High-Speed I/O Receiver Circuitry x
4.1.1. Soft Deserializer 4.1.2. Data Realignment Block (Bit Slip)
4.2. LVDS Receiver I/O Termination Schemes x
4.2.1. LVDS, Mini-LVDS, and RSDS Receiver External Termination 4.2.2. SLVS Receiver External Termination 4.2.3. Sub-LVDS Receiver External Termination 4.2.4. TMDS Receiver External Termination 4.2.5. HiSpi Receiver External Termination 4.2.6. LVPECL External Termination
4.3. LVDS Receiver FPGA Design Implementation x
4.3.1. Soft LVDS IP Core in Receiver Mode 4.3.2. High-Speed I/O Timing Budget 4.3.3. Guidelines: Floating LVDS Input Pins 4.3.4. Guidelines: LVDS Receiver Channels Placement 4.3.5. Guidelines: LVDS Channels PLL Placement 4.3.6. Guidelines: LVDS Receiver Logic Placement
4.3.1. Soft LVDS IP Core in Receiver Mode x
4.3.1.1. PLL Source Selection for Soft LVDS IP Core 4.3.1.2. Guidelines: LVDS RX Interface Using External PLL 4.3.1.3. Initializing the Soft LVDS IP Core
4.3.1.1. PLL Source Selection for Soft LVDS IP Core x
4.3.1.1.1. Instantiate Soft LVDS IP Core with Internal PLL 4.3.1.1.2. Instantiate Soft LVDS IP Core with External PLL
4.3.1.2. Guidelines: LVDS RX Interface Using External PLL x
4.3.1.2.1. ALTPLL Signal Interface with Soft LVDS Receiver 4.3.1.2.2. Determining External PLL Clock Parameters for Soft LVDS Receiver
4.3.2. High-Speed I/O Timing Budget x
4.3.2.1. Receiver Input Skew Margin 4.3.2.2. Guidelines: LVDS Receiver Timing Constraints
4.3.2.1. Receiver Input Skew Margin x
4.3.2.1.1. RSKM Equation 4.3.2.1.2. Example: RSKM Calculation
4.4. LVDS Receiver Debug and Troubleshooting x
4.4.1. Perform RTL Simulation Before Hardware Debug 4.4.2. Geometry-Based and Physics-Based I/O Rules
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design x
5.1. Transmitter–Receiver Interfacing 5.2. LVDS Transmitter and Receiver FPGA Design Implementation 5.3. LVDS Transmitter and Receiver Debug and Troubleshooting
5.2. LVDS Transmitter and Receiver FPGA Design Implementation x
5.2.1. LVDS Transmitter and Receiver PLL Sharing Implementation 5.2.2. Initializing the Soft LVDS IP Core
5.3. LVDS Transmitter and Receiver Debug and Troubleshooting x
5.3.1. Perform RTL Simulation Before Hardware Debug 5.3.2. Geometry-Based and Physics-Based I/O Rules
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations x
6.1. Guidelines: Improve Signal Quality 6.2. Guidelines: Control Channel-to-Channel Skew 6.3. Guidelines: Determine Board Design Constraints 6.4. Guidelines: Perform Board Level Simulations
7. Soft LVDS IP Core References x
7.1. Soft LVDS Parameter Settings 7.2. Soft LVDS Interface Signals
1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide

7.2. Soft LVDS Interface Signals

Depending on parameter settings you specify, different signals are available for the Soft LVDS IP core.
Table 15.  Transmitter Interface Signals
Signal Name Direction Width (Bit) Description
pll_areset Input 1

Asynchronously resets all counters to the initial values.

tx_data_reset Input <n>

Asynchronous reset for the shift registers, capture registers, and synchronization registers for all channels.

  • This signal is used if Use external PLL parameter setting is turned on.
  • This signal does not affect the data realignment block or the PLL.
tx_in[] Input <m>

This signal is parallel data that Soft LVDS IP core transmits serially.

Input data is synchronous to the tx_coreclock signal. The data bus width per channel is the same as the serialization factor (SF).

tx_inclock Input 1

Reference clock input for the transmitter PLL.

The parameter editor automatically selects the appropriate PLL multiplication factor based on the data and reference clock frequency.

tx_coreclock Output 1

Output clock that feeds non-peripheral logic.

FPGA fabric–transmitter interface clock—the parallel transmitter data generated in the FPGA fabric is clocked with this clock.

tx_locked Output 1

Provides the LVDS PLL status:

  • Remains high when the PLL is locked to the input reference clock.
  • Remains low when the PLL fails to lock.
tx_out[] Output <n>

Serialized LVDS data output signal of <n> channels.

tx_out[(<n>-1)..0] drives parallel data from tx_in[(<J> × <n>)-1 ..0] where <J> is the serialization factor and <n> is the number of channels. tx_out[0] drives data from tx_in[(<J>-1)..0]. tx_out[1] drives data from the next <J> number of bits on tx_in.

tx_outclock Output 1

External reference clock.

The frequency of this clock is programmable to be the same as the data rate.

Table 16.   Receiver Interface Signals

signal Name

Direction

Width (Bit)

Description

rx_data_reset Input <n>

Asynchronous reset for all channels, excluding the PLL.

  • This signal is available if Use external PLL parameter setting is turned on.
  • You must externally synchronize this signal with the fast clock.
rx_in[] Input <n>

LVDS serial data input signal of <n> channels.

rx_in[(<n>-1)..0] is deserialized and driven on rx_out[(<J> × <n>)-1 ..0] where <J> is the deserialization factor and <n> is the number of channels. rx_in[0] drives data to rx_out[(<J>-1)..0]. rx_in[1] drives data to the next <J> number of bits on rx_out.

rx_inclock Input 1

LVDS reference input clock.

The parameter editor automatically selects the appropriate PLL multiplication factor based on the data rate and reference clock frequency selection.

rx_coreclk Input <n>

LVDS reference input clock.

  • Replaces the non-peripheral clock from the PLL.
  • One clock for each channel.
rx_locked Output 1

Provides the LVDS PLL status:

  • Stays high when the PLL is locked to the input reference clock.
  • Stays low when the PLL fails to lock.
rx_out Output <m>

Receiver parallel data output.

The data bus width per channel is the same as the deserialization factor (DF).

rx_outclock Output 1

Parallel output clock from the receiver PLL.

  • This signal is not available if you turn on the Use external PLL parameter setting.
  • The FPGA fabric–receiver interface clock must be driven by the PLL instantiated through the ALTPLL parameter editor.
rx_data_align Input 1

Controls the byte alignment circuitry.

You can register this signal using the rx_outclock signal.

rx_data_align_reset Input 1

Resets the byte alignment circuitry.

Use the rx_data_align_reset input signal if:

  • You need to reset the PLL during device operation.
  • You need to re-establish the word alignment.
rx_channel_data_align Input <n>

Controls byte alignment circuitry.

rx_cda_reset Input <n>

Asynchronous reset to the data realignment circuitry. This signal resets the data realignment block.

The minimum pulse width requirement for this reset is one parallel clock cycle.

Level Two Title