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1. Intel® MAX® 10 High-Speed LVDS I/O Overview
2. Intel® MAX® 10 High-Speed LVDS Architecture and Features
3. Intel® MAX® 10 LVDS Transmitter Design
4. Intel® MAX® 10 LVDS Receiver Design
5. Intel® MAX® 10 LVDS Transmitter and Receiver Design
6. Intel® MAX® 10 High-Speed LVDS Board Design Considerations
7. Soft LVDS IP Core References
8. Intel® MAX® 10 High-Speed LVDS I/O User Guide Archives
9. Document Revision History for Intel® MAX® 10 High-Speed LVDS I/O User Guide
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3.4.4. Guidelines: LVDS Channels PLL Placement4.3.5. Guidelines: LVDS Channels PLL Placement
Each PLL in the Intel® MAX® 10 device can drive only the LVDS channels in I/O banks on the same edge as the PLL.
I/O Bank Edge | Input refclk | GCLK mux | Usable PLL |
---|---|---|---|
Left | Left | Left | Top left or bottom left |
Bottom | Bottom | Bottom | Bottom left or bottom right |
Right | Right | Right | Top right or bottom right |
Top | Top | Top | Top left or top right |