Intel® MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

5.1. GPIO Lite Intel® FPGA IP Parameter Settings

You can set the parameter settings for the GPIO Lite IP core in the Intel® Quartus® Prime software. There are three groups of options: General, Buffer, and Registers.
Table 26.   GPIO Lite Parameters - General
Parameter Condition Allowed Values Description
Data direction —
  • input
  • output
  • bidir

Specifies the data direction for the GPIO.

Data width —

1 to 128

Specifies the data width.

Table 27.   GPIO Lite Parameters - Buffer
Parameter Condition Allowed Values Description
Use true differential buffer Data direction = input or output
  • On
  • Off

If turned on, enables true differential I/O buffers and disables pseudo differential I/O buffers.

Use pseudo differential buffer Data direction = output or bidir
  • On
  • Off
  • If turned on in output mode—enables pseudo differential output buffers and disables true differential I/O buffers.
  • If turned on in bidir mode—enables true differential input buffer and pseudo differential output buffer.
Use bus-hold circuitry Data direction = input or output
  • On
  • Off

If turned on, the bus hold circuitry can weakly hold the signal on an I/O pin at its last-driven state where the output buffer state is 1 or 0 but not high-impedance.

Use open drain output Data direction = output or bidir
  • On
  • Off

If turned on, the open drain output enables the device to provide system-level control signals such as interrupt and write enable signals that can be asserted by multiple devices in your system.

Enable oe port Data direction = output
  • On
  • Off

If turned on, enables user input to the OE port. This option is automatically turned on for bidirectional mode.

Enable nsleep port (only available in selected devices) Data direction = input or bidir
  • On
  • Off

If turned on, enables the nsleep port.

This option is available for the 10M16, 10M25, 10M40, and 10M50 devices.

Table 28.   GPIO Lite Parameters - Registers
Parameter Condition Allowed Values Description
Register mode —
  • bypass
  • single-register
  • ddr
Specifies the register mode for the GPIO Lite IP core:
  • bypass—specifies a simple wire connection from/to the buffer.
  • single-register—specifies that the DDIO is used as a simple register in single data-rate mode (SDR). The Fitter may pack this register in the I/O.
  • ddr— specifies that the IP core uses the DDIO.
Enable aclr port
  • Register mode = ddr
  • On
  • Off

If turned on, enables the ACLR port for asynchronous clears.

Enable aset port
  • Data direction = output or bidir
  • Register mode = ddr
  • Set registers to power up high (when aclr and aset ports are not used) = off
  • On
  • Off

If turned on, enables the ASET port for asynchronous preset.

Set registers to power up high (when aclr and aset ports are not used)
  • Register mode = ddr
  • Enable aclr port = off
  • Enable aset port = off
  • Enable sclr port = off
  • On
  • Off

If you are not using the ACLR and ASET ports:

  • On—specifies that registers power up HIGH.
  • Off—specifies that registers power up LOW.
Enable inclocken/outclocken ports Register mode = ddr
  • On
  • Off
  • On—exposes the clock enable port to allow you to control when data is clocked in or out. This signal prevents data from being passed through without your control.
  • Off—clock enable port is not exposed and data always pass through the register automatically.
Invert din
  • Data direction = output
  • Register mode = ddr
  • On
  • Off

If turned on, inverts the data out output port.

Invert DDIO inclock
  • Data direction = input or bidir
  • Register mode = ddr
  • On
  • Off
  • On—captures the first data bit on the falling edge of the input clock.
  • Off—captures the first data bit on the rising edge of the input clock.
Use a single register to drive the output enable (oe) signal at the I/O buffer
  • Data direction = output or bidir
  • Register mode = single-register or ddr
  • Use DDIO registers to drive the output enable (oe) signal at the I/O buffer = off
  • On
  • Off

If turned on, specifies that a single register drives the OE signal at the output buffer.

Use DDIO registers to drive the output enable (oe) signal at the I/O buffer
  • Data direction = output or bidir
  • Register mode = ddr
  • Use a single register to drive the output enable (oe) signal at the I/O buffer = off
  • On
  • Off

If turned on, specifies that the DDR I/O registers drive the OE signal at the output buffer. The output pin is held at high impedance for an extra half clock cycle after the OE port goes high.

Implement DDIO input registers in hard implementation (Only available in certain devices)
  • Data direction = input or bidir
  • Register mode = ddr
  • On
  • Off
  • On—implements the DDIO input registers using hard block at the I/O edge.
  • Off—implements the DDIO input registers as soft implementation using registers in the FPGA core fabric.

This option is applicable only for Intel® MAX® 10 16, 25, 40, and 50 devices because the DDIO input registers hard block is available only in these devices. To avoid Fitter error, turn this option off for other Intel® MAX® 10 devices.

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