1.2. Directory Structure
The Low Latency E-Tile 40G Ethernet IP core design example file directories contain the following generated files for the design example.
Figure 4. Directory Structure for the Generated Design Example
- The simulation files (testbench for simulation only) are located in <design_example_dir>/example_testbench.
- The compilation-only example design is located in <design_example_dir>/compilation_test_design.
- The hardware configuration and test files (the hardware design example) are located in <design_example_dir>/hardware_test_design.
File Names |
Description |
---|---|
eth_ex_40g.qpf | Quartus® Prime project file. |
eth_ex_40g.qsf | Quartus® Prime project settings file. |
eth_ex_40g.sdc | Synopsys* Design Constraints file. You can copy and modify this file for your own Low Latency E-Tile 40G Ethernet Intel® FPGA IP design. |
eth_ex_40g.srf | Quartus® Prime project message suppression rule file. |
eth_ex_40g.v | Top-level Verilog HDL design example file. |
eth_ex_40g_clock.sdc | Synopsys* Design Constraints file for clocks. |
common/ | Hardware design example support files. |
hwtest/main.tcl | Main file for accessing System Console. |