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1.1. Generating the Design Example
1.2. Directory Structure
1.3. Simulating the Design Example Testbench
1.4. Compiling and Configuring the Design Example in Hardware
1.5. Changing Target Device in Hardware Design Example
1.6. Testing the Low Latency E-Tile 40G Ethernet Intel® FPGA IP Design in Hardware
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Ixiasoft
1.4. Compiling and Configuring the Design Example in Hardware
The Intel® FPGA IP core parameter editor allows you to compile and configure the design example on a target development kit.
- Launch the Quartus® Prime Pro Edition software and select Processing > Start Compilation to compile the design.
- After you generate an SRAM object file .sof, follow these steps to program the hardware design example on the Intel device:
- Select Tools > Programmer.
- In the Programmer, click Hardware Setup.
- Select a programming device.
- Select and add the Intel TX board to your Quartus® Prime Pro Edition session.
- Ensure that Mode is set to JTAG.
- Select the Intel device and click Add Device. The Programmer displays a block diagram of the connections between the devices on your board.
- In the row with your .sof, check the box for the .sof.
- Turn on Program/Configure option for the .sof.
- Click Start.