Visible to Intel only — GUID: nik1410564885691
Ixiasoft
Visible to Intel only — GUID: nik1410564885691
Ixiasoft
4.13.4. PIPE Interface Signals
These PIPE signals are available for Gen1 and Gen2 variants so that you can simulate using either the serial or the PIPE interface. Simulation is much faster using the PIPE interface because the PIPE simulation bypasses the SERDES model . By default, the PIPE interface is 8 bits for Gen1 and Gen2. You can use the PIPE interface for simulation even though your actual design includes a serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in hardware, including probing these signals using SignalTap® II Embedded Logic Analyzer.
Signal |
Direction |
Description |
---|---|---|
txdata0[7:0] | Output |
Transmit data <n> (2 symbols on lane <n>). This bus transmits data on lane <n>. |
txdatak0 | Output |
Transmit data control <n>. This signal serves as the control bit for txdata <n>. |
txdetectrx0 |
Output |
Transmit detect receive <n>. This signal tells the PHY layer to start a receive detection operation or to begin loopback. |
txelecidle0 |
Output |
Transmit electrical idle <n>. This signal forces the TX output to electrical idle. |
txcompl0 |
Output |
Transmit compliance <n>. This signal forces the running disparity to negative in Compliance Mode (negative COM character). |
rxpolarity0 |
Output |
Receive polarity <n>. This signal instructs the PHY layer to invert the polarity of the 8B/10B receiver decoding block. |
powerdown0[1:0] |
Output |
Power down <n>. This signal requests the PHY to change its power state to the specified state (P0, P0s, P1, or P2). |
tx_deemph0 | Output |
Transmit de-emphasis selection. The Arria V Hard IP for PCI Express sets the value for this signal based on the indication received from the other end of the link during the Training Sequences (TS). You do not need to change this value. |
rxdata0[7:0] (1) |
Input |
Receive data <n> (2 symbols on lane <n>). This bus receives data on lane <n>. |
rxdatak0 (1) |
Input |
Receive data >n>. This bus receives data on lane <n>. |
rxvalid0 (1) |
Input |
Receive valid <n>. This signal indicates symbol lock and valid data on rxdata <n> and rxdatak <n>. |
phystatus0 (1) |
Input |
PHY status <n>. This signal communicates completion of several PHY requests. |
eidleinfersel0[2:0] | Output |
Electrical idle entry inference mechanism selection. The following encodings are defined:
|
rxelecidle0 (1) |
Input |
Receive electrical idle <n>. When asserted, indicates detection of an electrical idle. |
rxstatus0[2:0] (1) |
Input |
Receive status <n>. This signal encodes receive status and error codes for the receive data stream and receiver detection. |
sim_pipe_ltssmstate0[4:0] | Input and Output |
LTSSM state: The LTSSM state machine encoding defines the following states:
|
sim_pipe_rate[1:0] | Output |
The 2‑bit encodings have the following meanings:
|
sim_pipe_pclk_in | Input |
This clock is used for PIPE simulation only, and is derived from the refclk. It is the PIPE interface clock used for PIPE mode simulation. |
txswing0 | Output |
When asserted, indicates full swing for the transmitter voltage. When deasserted indicates half swing. |
tx_margin0[2:0] |
Output |
Transmit VOD margin selection. The value for this signal is based on the value from the Link Control 2 Register. Available for simulation only. |
Notes:
|