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1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Arria V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer
4.2. Clock Signals
4.3. Reset Signals
4.4. Hard IP Status
4.5. Error Signals
4.6. ECRC Forwarding
4.7. Interrupts for Endpoints
4.8. Interrupts for Root Ports
4.9. Completion Side Band Signals
4.10. Transaction Layer Configuration Space Signals
4.11. LMI Signals
4.12. Power Management Signals
4.13. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. Uncorrectable Internal Error Mask Register
5.8. Uncorrectable Internal Error Status Register
5.9. Correctable Internal Error Mask Register
5.10. Correctable Internal Error Status Register
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
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6.1.3. Implementing MSI-X Interrupts
Section 6.8.2 of the PCI Local Bus Specification describes the MSI-X capability and table structures. The MSI-X capability structure points to the MSI-X Table structure and MSI-X Pending Bit Array (PBA) registers. The BIOS sets up the starting address offsets and BAR associated with the pointer to the starting address of the MSI-X Table and PBA registers.
MSI-X Interrupt Components
- Host software sets up the MSI-X interrupts in the Application Layer by completing the following steps:
- Host software reads the Message Control register at 0x050 register to determine the MSI-X Table size. The number of table entries is the <value read> + 1.
The maximum table size is 2048 entries. Each 16-byte entry is divided in 4 fields as shown in the figure below. The MSI-X table can be accessed on any BAR configured. The base address of the MSI-X table must be aligned to a 4 KB boundary.
- The host sets up the MSI-X table. It programs MSI-X address, data, and masks bits for each entry as shown in the figure below.
Figure 57. Format of MSI-X Table
- The host calculates the address of the <n th > entry using the following formula:
nth_address = base address[BAR] + 16<n>
- Host software reads the Message Control register at 0x050 register to determine the MSI-X Table size. The number of table entries is the <value read> + 1.
- When Application Layer has an interrupt, it drives an interrupt request to the IRQ Source module.
- The IRQ Source sets appropriate bit in the MSI-X PBA table.
The PBA can use qword or dword accesses. For qword accesses, the IRQ Source calculates the address of the <m th > bit using the following formulas:
qword address = <PBA base addr> + 8(floor(<m>/64)) qword bit = <m> mod 64
Figure 58. MSI-X PBA Table - The IRQ Processor reads the entry in the MSI-X table.
- If the interrupt is masked by the Vector_Control field of the MSI-X table, the interrupt remains in the pending state.
- If the interrupt is not masked, IRQ Processor sends Memory Write Request to the TX slave interface. It uses the address and data from the MSI-X table. If Message Upper Address = 0, the IRQ Processor creates a three-dword header. If the Message Upper Address > 0, it creates a 4-dword header.
- The host interrupt service routine detects the TLP as an interrupt and services it.