Arria V Avalon-ST Interface for PCIe Solutions User Guide

ID 683733
Date 1/04/2023
Public
Document Table of Contents

4.1.1.2. Data Alignment and Timing for the 64‑Bit Avalon® -ST RX Interface

To facilitate the interface to 64-bit memories, the Arria V Hard IP for PCI Express aligns data to the qword or 64 bits by default. Consequently, if the header presents an address that is not qword aligned, the Hard IP block shifts the data within the qword to achieve the correct alignment.

Qword alignment applies to all types of request TLPs with data, including the following TLPs:

  • Memory writes
  • Configuration writes
  • I/O writes

The alignment of the request TLP depends on bit 2 of the request address. For completion TLPs with data, alignment depends on bit 2 of the lower address field. This bit is always 0 (aligned to qword boundary) for completion with data TLPs that are for configuration read or I/O read requests.

Figure 12. Qword AlignmentThe following figure shows how an address that is not qword aligned, 0x4, is stored in memory. The byte enables only qualify data that is being written. This means that the byte enables are undefined for 0x0–0x3. This example corresponds to 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Non-Qword Aligned Address.

The following table shows the byte ordering for header and data packets.

Table 25.  Mapping Avalon-ST Packets to PCI Express TLPs

Packet

TLP

Header0

pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3

Header1

pcie_hdr _byte4, pcie_hdr _byte5, pcie_hdr byte6, pcie_hdr _byte7

Header2

pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11

Header3

pcie_hdr _byte12, pcie_hdr _byte13, header_byte14, pcie_hdr _byte15

Data0

pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0

Data1

pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4

Data2

pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8

Data<n>

pcie_data_byte<4n+3>, pcie_data_byte<4n+2>, pcie_data_byte<4n+1>, pcie_data_byte<n>

The following figure illustrates the mapping of Avalon‑ST RX packets to PCI Express TLPs for a three dword header with non-qword aligned addresses with a 64-bit bus. In this example, the byte address is unaligned and ends with 0x4, causing the first data to correspond to rx_st_data[63:32] .

Note: The Avalon-ST protocol, as defined in Avalon Interface Specifications, is big endian, while the Hard IP for PCI Express packs symbols into words in little endian format. Consequently, you cannot use the standard data format adapters available in Platform Designer.
Figure 13. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Non-Qword Aligned Address

The following figure illustrates the mapping of Avalon-ST RX packets to PCI Express TLPs for a three dword header with qword aligned addresses. Note that the byte enables indicate the first byte of data is not valid and the last dword of data has a single valid byte.

Figure 14. 64-Bit Avalon-ST rx_st_data<n> Cycle Definition for 3-Dword Header TLPs with Qword Aligned Address In the following figure, rx_st_be[7:4] corresponds to rx_st_data[63:32]. rx_st_be[3:0] corresponds to rx_st_data[31:0].
Figure 15. 64-Bit Application Layer Backpressures Transaction Layer The following figure illustrates the timing of the RX interface when the Application Layer backpressures the Arria V Hard IP for PCI Express by deasserting rx _st_ready. The rx_st_valid signal deasserts within three cycles after rx_st_ready is deasserted. In this example, rx_st_valid is deasserted in the next cycle. rx_st_data is held until the Application Layer is able to accept it.
Figure 16. 64-Bit Avalon-ST Interface Back-to-Back Transmission

The following figure illustrates back‑to‑back transmission on the 64‑bit Avalon‑ST RX interface with no idle cycles between the assertion of rx_st_eop and rx_st_sop.