Visible to Intel only — GUID: nik1410565005435
Ixiasoft
1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Arria V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer
4.2. Clock Signals
4.3. Reset Signals
4.4. Hard IP Status
4.5. Error Signals
4.6. ECRC Forwarding
4.7. Interrupts for Endpoints
4.8. Interrupts for Root Ports
4.9. Completion Side Band Signals
4.10. Transaction Layer Configuration Space Signals
4.11. LMI Signals
4.12. Power Management Signals
4.13. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. Uncorrectable Internal Error Mask Register
5.8. Uncorrectable Internal Error Status Register
5.9. Correctable Internal Error Mask Register
5.10. Correctable Internal Error Status Register
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
Visible to Intel only — GUID: nik1410565005435
Ixiasoft
15.4. Root Port Design Example
The design example includes the following primary components:
- Root Port variation (<qsys_systemname>.
- Avalon-ST Interfaces (altpcietb_bfm_vc_intf_ast)—handles the transfer of TLP requests and completions to and from the Arria V Hard IP for PCI Express variation using the Avalon‑ST interface.
- Root Port BFM tasks—contains the high-level tasks called by the test driver, low‑level tasks that request PCI Express transfers from altpcietb_bfm_vc_intf_ast, the Root Port memory space, and simulation functions such as displaying messages and stopping simulation.
- Test Driver (altpcietb_bfm_driver_rp.v)—the chaining DMA Endpoint test driver which configures the Root Port and Endpoint for DMA transfer and checks for the successful transfer of data. Refer to the Test Driver Modulefor a detailed description.
Figure 75. Root Port Design Example
You can use the example Root Port design for Verilog HDL simulation. All of the modules necessary to implement the example design with the variation file are contained in altpcietb_bfm_ep_example_chaining_pipen1b.v.
The top-level of the testbench instantiates the following key files:
- altlpcietb_bfm_top_ep.v— this is the Endpoint BFM. This file also instantiates the SERDES and PIPE interface.
- altpcietb_pipe_phy.v—used to simulate the PIPE interface.
- altp cietb_bfm_ep_example_chaining_pipen1b.v—the top-level of the Root Port design example that you use for simulation. This module instantiates the Root Port variation, <variation_name> .v, and the Root Port application altpcietb_bfm_vc_intf _<application_width> . This module provides both PIPE and serial interfaces for the simulation environment. This module has two debug ports named test_out_icm_(which is the test_out signal from the Hard IP) and test_in which allows you to monitor and control internal states of the Hard IP variation.
- altpcietb_bfm_vc_intf_ast.v—a wrapper module which instantiates either altpcietb_vc_intf_64 or altpcietb_vc_intf_ <application_width> based on the type of Avalon‑ST interface that is generated.
- altpcietb_vc_intf_ _<application_width> .v—provide the interface between the Arria V Hard IP for PCI Express variant and the Root Port BFM tasks. They provide the same function as the altpcietb_bfm_vc_intf.v module, transmitting requests and handling completions. Refer to the Root Port BFM for a full description of this function. This version uses Avalon‑ST signaling with either a 64- or 128-bit data bus interface.
- altpcierd_tl_cfg_sample.v—accesses Configuration Space signals from the variant. Refer to the Chaining DMA Design Examples for a description of this module.
Files in subdirectory <qsys_systemname> /testbench/simulation/submodules:
- altpcietb_bfm_ep_example_chaining_pipen1b.v—the simulation model for the chaining DMA Endpoint.
- altpcietb_bfm_driver_rp.v–this file contains the functions to implement the shared memory space, PCI Express reads and writes, initialize the Configuration Space registers, log and display simulation messages, and define global constants.
Related Information