Visible to Intel only — GUID: nik1410564868721
Ixiasoft
Visible to Intel only — GUID: nik1410564868721
Ixiasoft
4.10. Transaction Layer Configuration Space Signals
Signal |
Direction |
Description |
---|---|---|
tl_cfg_add[6:0] | 0utput |
Address of the register that has been updated. This signal is an index indicating which Configuration Space register information is being driven onto tl_cfg_ctl. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl . The index increments every 8coreclkout cycle. The index increments every 8 coreclkout cycles. The index consists of the following 2 fields:
|
tl_cfg_ctl[31:0] | 0utput |
The signal is multiplexed and contains the contents of the Configuration Space registers. The indexing is defined in Multiplexed Configuration Register Information Available on tl_cfg_ctl . |
tl_cfg_ctl_wr | 0utput |
Write signal. This signal toggles when tl_cfg_ctl has been updated (every 8 coreclkout cycles). The toggle edge marks where the tl_cfg_ctl data changes. You can use this edge as a reference to determine when the data is safe to sample. |
tl_cfg_sts[122:0] | 0utput |
Configuration status bits. This information updates every coreclkout cycle. Bits[52:0] record status information for function0. Bits[62:53] record information for function1. Bits[72:63] record information for function 2, and so on. Refer to the following table for a detailed description of the status bits. |
tl_cfg_sts_wr | 0utput |
Write signal. This signal toggles when tl_cfg_stshas been updated (every 8 core_clk cycles). The toggle marks the edge where tl_cfg_sts data changes. You can use this edge as a reference to determine when the data is safe to sample. |
hpg_ctrler[4:0] | Input |
The hpg_ctrler signals are only available in Root Port mode and when the Slot capability register is enabled. Refer to the Slot register and Slot capability register parameters in Table 6–9 on page 6–10. For Endpoint variations the hpg_ctrler input should be hardwired to 0s. The bits have the following meanings: |
Input |
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|
Input |
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|
Input |
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Input |
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Input |
|
tl_cfg_sts |
Configuration Space Register |
Description |
---|---|---|
[62:59] Func1 [72:69] Func2 [82:79] Func3 [92:89] Func4 [102:99] Func5 [112:109] Func6 [122:119] Func7 |
Device Status Reg[3:0] |
Records the following errors:
|
[58:54] Func1 [68:64] Func2 [78:74] Func3 [88:84] Func4 [98:94] Func5 [108:104] Func6 [118:114] Func7 |
Link Status Reg[15:11] |
Link status bits as follows:
|
[53] Func1 [63] Func2 [73] Func3 [83] Func4 [93] Func5 [103] Func6 [113] Func7 |
Secondary Status Reg[8] |
6th primary command status error bit. Master data parity error. |
[52:49] |
Device Status Reg[3:0] |
Records the following errors:
|
[48] |
Slot Status Register[8] |
Data Link Layer state changed |
[47] | Slot Status Reg[4] |
Command completed. (The hot plug controller completed a command.) |
[46:31] |
Link Status Reg[15:0] |
Records the following link status information:
|
[30] |
Link Status 2 Reg[0] |
Current de-emphasis level. |
[29:25] |
Status Reg[15:11] |
Records the following 5 primary command status errors:
|
[24] |
Secondary Status Reg[8] |
Master data parity error |
[23:6] |
Root Status Reg[17:0] |
Records the following PME status information:
|
[5:1] |
Secondary Status Reg[15:11] |
Records the following 5 secondary command status errors:
|
[0] |
Secondary Status Reg[8] |
Master Data Parity Error |