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Ixiasoft
3.1. Avalon-ST System Settings
Parameter |
Value |
Description |
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Number of Lanes |
×1, ×2, ×4, ×8 |
Specifies the maximum number of lanes supported. |
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Lane Rate |
Gen1 (2.5 Gbps) Gen2 (2.5/5.0 Gbps) |
Specifies the maximum data rate at which the link can operate. |
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Port type |
Root Port Native Endpoint Legacy Endpoint |
Specifies the port type. Altera recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility. The Legacy Endpoint is not available for the Avalon‑MM Arria V Hard IP for PCI Express. The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configuration Space. |
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Application Interface |
Avalon-ST 64-bit Avalon-ST 128-bit |
Specifies the width of the Avalon-ST interface between the Application and Transaction Layers. The following widths are required:
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RX Buffer credit allocation -performance for received requests |
Minimum Low Balanced High Maximum |
Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KByte RX buffer. The 5 settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane. Refer to the Throughput Optimization chapter for more information about optimizing performance. The Flow Control chapter explains how the RX credit allocation and the Maximum payload RX Buffer credit allocation and the Maximum payload size that you choose affect the allocation of flow control credits. You can set the Maximum payload size parameter on the Device tab. The Message window of the GUI dynamically updates the number of credits for Posted, Non‑Posted Headers and Data, and Completion Headers and Data as you change this selection.
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Reference clock frequency |
100 MHz 125 MHz |
The PCI Express Base Specification requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. |
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Use 62.5 MHz application clock |
On/Off |
This mode is only available only for Gen1 ×1. |
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Use deprecated RX Avalon-ST data byte enable port (rx_st_be) |
On/Off |
This parameter is only available for the Avalon‑ST Arria V Hard IP for PCI Express. |
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Enable configuration via PCIe link |
On/Off |
When On, the Quartus® Prime software places the Endpoint in the location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below. |
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Enable Hard IP Reconfiguration |
On/Off |
When On, you can use the Hard IP reconfiguration bus to dynamically reconfigure Hard IP read‑only registers. For more information refer to Hard IP Reconfiguration Interface. This parameter is not available for the Avalon-MM IP Cores. |
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Number of Functions |
1–8 | Specifies the number of functions that share the same link. |