Visible to Intel only — GUID: nik1410564880717
Ixiasoft
Visible to Intel only — GUID: nik1410564880717
Ixiasoft
4.13.2.1. Physical Layout of Hard IP in Arria V Devices
Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files for Intel Devices.
Channel utilization for x1, x2, x4, and x8 variants is as follows:
Variant | Data | CMU Clock |
---|---|---|
x1, 1 instance | Channel 0 of GXB_L0 | Channel 1 of GXB_L0 |
x1, 2 instances | Channel 0 of GXB_L0, Channel 0 of GXB_R0 | Channel 1 of GXB_L0, Channel 1 of GXB_R0 |
x2, 1 instance | Channels 1–2 of GXB_L0 | Channel 4 of GXB_L0 |
x2, 2 instances | Channels 1–2 of GXB_L0, Channels 1–2 of GXB_R0 | Channel 4 of GXB_L0, Channel 4 of GXB_R0 |
x4, 1 instance | Channels 0–3 of GXB_L0 | Channel 4 of GXB_L0 |
x4, 2 instances | Channels 0–3 of GXB_L0, Channels 0–3 of GXB_R0 | Channel 4 of GXB_L0, Channel 4 of GXB_R0 |
x8, 1 instance | Channels 0–3 and 5 of GXB_L0 and channels 0-2 of GXB_L1 | Channel 4 of GXB_L0 |