Arria V Avalon-ST Interface for PCIe Solutions User Guide

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ID 683733
Date 1/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Arria V Hard IP for PCI Express 3. Parameter Settings 4. Interfaces and Signal Descriptions 5. Registers 6. Interrupts 7. Error Handling 8. IP Core Architecture 9. Transaction Layer Protocol (TLP) Details 10. Throughput Optimization 11. Design Implementation 12. Additional Features 13. Hard IP Reconfiguration 14. Transceiver PHY IP Reconfiguration 15. Testbench and Design Example 16. Debugging A. Transaction Layer Packet (TLP) Header Formats B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Arria V Avalon-ST Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Example Designs 1.7. Debug Features 1.8. IP Core Verification 1.9. Performance and Resource Utilization 1.10. Recommended Speed Grades 1.11. Creating a Design for PCI Express
1.8. IP Core Verification x
1.8.1. Compatibility Testing Environment
2. Getting Started with the Arria V Hard IP for PCI Express x
2.1. Qsys Design Flow 2.2. Modifying the Example Design 2.3. Using the IP Catalog To Generate Your Arria V Hard IP for PCI Express as a Separate Component
2.1. Qsys Design Flow x
2.1.1. Generating the Testbench 2.1.2. Simulating the Example Design 2.1.3. Generating Synthesis Files 2.1.4. Understanding the Files Generated 2.1.5. Understanding Physical Placement of the PCIe IP Core 2.1.6. Compiling the Design in the Quartus® Prime Software
3. Parameter Settings x
3.1. Avalon-ST System Settings 3.2. Link Capabilities 3.3. Port Function Parameters Shared Across All Port Functions 3.4. Port Function Parameters Defined Separately for All Port Functions
3.3. Port Function Parameters Shared Across All Port Functions x
3.3.1. Device Capabilities 3.3.2. Error Reporting 3.3.3. Link Capabilities 3.3.4. Slot Capabilities 3.3.5. Power Management
3.4. Port Function Parameters Defined Separately for All Port Functions x
3.4.1. Base Address Register (BAR) and Expansion ROM Settings 3.4.2. Base and Limit Registers for Root Ports 3.4.3. Device Identification Registers for Function <n> 3.4.4. Func <n> Device 3.4.5. Func <n> Link 3.4.6. Func <n> MSI and MSI-X Capabilities 3.4.7. Func <n> Legacy Interrupt
4. Interfaces and Signal Descriptions x
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer 4.2. Clock Signals 4.3. Reset Signals 4.4. Hard IP Status 4.5. Error Signals 4.6. ECRC Forwarding 4.7. Interrupts for Endpoints 4.8. Interrupts for Root Ports 4.9. Completion Side Band Signals 4.10. Transaction Layer Configuration Space Signals 4.11. LMI Signals 4.12. Power Management Signals 4.13. Physical Layer Interface Signals
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer x
4.1.1. Avalon‑ST RX Interface 4.1.2. Avalon-ST TX Interface
4.1.1. Avalon‑ST RX Interface x
4.1.1.1. Avalon-ST RX Component Specific Signals 4.1.1.2. Data Alignment and Timing for the 64‑Bit Avalon® -ST RX Interface 4.1.1.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST RX Interface
4.1.2. Avalon-ST TX Interface x
4.1.2.1. Avalon-ST Packets to PCI Express TLPs 4.1.2.2. Data Alignment and Timing for the 64‑Bit Avalon-ST TX Interface 4.1.2.3. Data Alignment and Timing for the 128‑Bit Avalon‑ST TX Interface 4.1.2.4. Root Port Mode Configuration Requests
4.10. Transaction Layer Configuration Space Signals x
4.10.1. Configuration Space Register Access Timing 4.10.2. Configuration Space Register Access
4.13. Physical Layer Interface Signals x
4.13.1. Transceiver Reconfiguration 4.13.2. Serial Interface Signals 4.13.3. Hard IP Reconfiguration Interface 4.13.4. PIPE Interface Signals 4.13.5. Test Signals
4.13.2. Serial Interface Signals x
4.13.2.1. Physical Layout of Hard IP in Arria V Devices 4.13.2.2. Channel Placement in Arria V Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. Uncorrectable Internal Error Mask Register 5.8. Uncorrectable Internal Error Status Register 5.9. Correctable Internal Error Mask Register 5.10. Correctable Internal Error Status Register
6. Interrupts x
6.1. Interrupts for Endpoints 6.2. Interrupts for Root Ports
6.1. Interrupts for Endpoints x
6.1.1. MSI Interrupts 6.1.2. MSI-X 6.1.3. Implementing MSI-X Interrupts
6.1.3. Implementing MSI-X Interrupts x
6.1.3.1. Legacy Interrupts
6.1.3.1. Legacy Interrupts x
6.1.3.1.1. Enabling MSI or Legacy Interrupts
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
8. IP Core Architecture x
8.1. Top-Level Interfaces 8.2. Transaction Layer 8.3. Data Link Layer 8.4. Physical Layer 8.5. Multi-Function Support
8.1. Top-Level Interfaces x
8.1.1. Avalon-ST Interface 8.1.2. Clocks and Reset 8.1.3. Local Management Interface (LMI Interface) 8.1.4. Hard IP Reconfiguration 8.1.5. Transceiver Reconfiguration 8.1.6. Interrupts 8.1.7. PIPE
8.2. Transaction Layer x
8.2.1. Configuration Space
9. Transaction Layer Protocol (TLP) Details x
9.1. Supported Message Types 9.2. Transaction Layer Routing Rules 9.3. Receive Buffer Reordering
9.1. Supported Message Types x
9.1.1. INTX Messages 9.1.2. Power Management Messages 9.1.3. Error Signaling Messages 9.1.4. Locked Transaction Message 9.1.5. Slot Power Limit Message 9.1.6. Vendor-Defined Messages 9.1.7. Hot Plug Messages
9.3. Receive Buffer Reordering x
9.3.1. Using Relaxed Ordering
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Design Implementation x
11.1. Making Analog QSF Assignments Using the Assignment Editor 11.2. Making Pin Assignments 11.3. Recommended Reset Sequence to Avoid Link Training Issues
12. Additional Features x
12.1. Configuration over Protocol (CvP) 12.2. Autonomous Mode 12.3. ECRC
12.2. Autonomous Mode x
12.2.1. Enabling Autonomous Mode 12.2.2. Enabling CvP Initialization
12.3. ECRC x
12.3.1. ECRC on the RX Path 12.3.2. ECRC on the TX Path
14. Transceiver PHY IP Reconfiguration x
14.1. Connecting the Transceiver Reconfiguration Controller IP Core 14.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
15. Testbench and Design Example x
15.1. Endpoint Testbench 15.2. Root Port Testbench 15.3. Test Driver Module 15.4. Root Port Design Example 15.5. Root Port BFM Overview 15.6. BFM Procedures and Functions 15.7. Setting Up Simulation
15.1. Endpoint Testbench x
15.1.1. Endpoint Testbench for SR-IOV
15.5. Root Port BFM Overview x
15.5.1. BFM Memory Map 15.5.2. Configuration Space Bus and Device Numbering 15.5.3. Configuration of Root Port and Endpoint 15.5.4. Issuing Read and Write Transactions to the Application Layer
15.6. BFM Procedures and Functions x
15.6.1. ebfm_barwr Procedure 15.6.2. ebfm_barwr_imm Procedure 15.6.3. ebfm_barrd_wait Procedure 15.6.4. ebfm_barrd_nowt Procedure 15.6.5. ebfm_cfgwr_imm_wait Procedure 15.6.6. ebfm_cfgwr_imm_nowt Procedure 15.6.7. ebfm_cfgrd_wait Procedure 15.6.8. ebfm_cfgrd_nowt Procedure 15.6.9. BFM Configuration Procedures 15.6.10. BFM Shared Memory Access Procedures 15.6.11. BFM Log and Message Procedures 15.6.12. Verilog HDL Formatting Functions
15.6.9. BFM Configuration Procedures x
15.6.9.1. ebfm_cfg_rp_ep Procedure 15.6.9.2. ebfm_cfg_decode_bar Procedure
15.6.10. BFM Shared Memory Access Procedures x
15.6.10.1. Shared Memory Constants 15.6.10.2. shmem_write Task 15.6.10.3. shmem_read Function 15.6.10.4. shmem_display Verilog HDL Function 15.6.10.5. shmem_fill Procedure 15.6.10.6. shmem_chk_ok Function
15.6.11. BFM Log and Message Procedures x
15.6.11.1. ebfm_display Verilog HDL Function 15.6.11.2. ebfm_log_stop_sim Verilog HDL Function 15.6.11.3. ebfm_log_set_suppressed_msg_mask Task 15.6.11.4. ebfm_log_set_stop_on_msg_mask Verilog HDL Task 15.6.11.5. ebfm_log_open Verilog HDL Function 15.6.11.6. ebfm_log_close Verilog HDL Function
15.6.12. Verilog HDL Formatting Functions x
15.6.12.1. himage1 15.6.12.2. himage2 15.6.12.3. himage4 15.6.12.4. himage8 15.6.12.5. himage16 15.6.12.6. dimage1 15.6.12.7. dimage2 15.6.12.8. dimage3 15.6.12.9. dimage4 15.6.12.10. dimage5 15.6.12.11. dimage6 15.6.12.12. dimage7
15.7. Setting Up Simulation x
15.7.1. Changing Between Serial and PIPE Simulation 15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants 15.7.3. Viewing the Important PIPE Interface Signals 15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations 15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations 15.7.6. Changing between the Hard and Soft Reset Controller
16. Debugging x
16.1. Hardware Bring-Up Issues 16.2. Link Training 16.3. Use Third-Party PCIe Analyzer 16.4. BIOS Enumeration Issues
16.2. Link Training x
16.2.1. Link Hangs in L0 State
A. Transaction Layer Packet (TLP) Header Formats x
A.1. TLP Packet Formats without Data Payload A.2. TLP Packet Formats with Data Payload
C. Document Revision History x
C.1. Document Revision History of the Arria V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide
1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Document Revision History

C.1. Document Revision History of the Arria V Avalon® Streaming (Avalon-ST) Interface for PCIe* Solutions User Guide

Date

Version

Changes Made

2021.06.03 18.0 Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture.
2020.12.21 18.0 Fixed broken links.
2020.06.02 18.0

Changed the clock associated with the tl_cfg_add[3:0] and tl_cfg_sts[52:0] to coreclkout_hip in the Transaction Layer Configuration Space Signals section.

Updated the Configuration Space Register Access Timing section to state that the tl_cfg_add[3:0] and tl_cfg_ctl[31:0] update every eight coreclkout_hip cycles.

2020.03.19 18.0 Updated reset sequence and descriptions in Reset and Clocks to show that reset_status is the output that can be used to drive the reset of the Application Layer logic.
2019.12.20 18.0 Changed the name of the 1A state for the ltssmstate[4:0] signals to Recovery.Speed to follow the PCIe Specifications.
2019.12.02 18.0 Changed the description of the parameter BAR Size for Legacy Endpoint variants from 6 Bytes - 4 KB to 16 Bytes - 4 KB (for I/O space BARs).
2019.10.09 18.0 Added the 1F state (Recovery.Equalization, Done) for ltssmstate[4:0].
2019.05.22 18.0 Added a note clarifying that the 24-bit Class Code register consists of three 8-bit fields: Base Class Code, Sub-Class Code and Programming Interface.
2019.05.03 18.0 Updated the diagram for the reset sequence of the Hard IP for PCI Express IP Core and Application Layer to reflect the real behavior of reset_status.
2019.01.18 18.0

Removed the High and Maximum options for the RX buffer allocation parameter because they are not supported.

Changed the readyLatency of the RX interface to 3 cycles.

2018.12.28 18.0 Added a note clarifying that the IP core can support up to 256 tags only when in Configuration Bypass mode.
2018.09.11 18.0 Updated the description for pld_clk in the Clock Signals and Clock Summary sections. Also updated the clock domain in the timing diagrams in the Data Alignment and Timing for the 64-Bit Avalon-ST TX Interface section.
2018.08.13 18.0 Added the step to invoke Vsim to the instructions for running a ModelSim simulation.
2018.05.07 18.0

Replaced all references to Intel® Cyclone® 10 with Intel® Cyclone® 10 GX.

2017.10.14 17.1

Corrected typo: added optional parameter to invert the RX polarity, not the TX polarity.

2017.10.06 17.1 Made the following changes to the user guide:
  • Added support for Intel® Cyclone® 10 GX devices.
  • Removed the Getting Started with the Hard IP for PCI Express with the Avalon-ST Interface. The PCIe Quick Start Guide which downloads to hardware replaces it.
  • Corrected signal name, tx_cred_cons_sel should be tx_cons_cred_sel.

  • Revised the Testbench and Design Example chapter. Although the functions and tasks that implement the testbench have not changed, the organization of these functions and task in files is entirely different than in earlier device families.

  • Fixed minor errors and typos.
2017.05.12 17.0

Made the following changes to the user guide:

  • Corrected definitions of tl_cfg_add[6:0] and tl_cfg_sts[122:0] under Transaction Layer Configuration Space Signals to include information for multi-function support.
  • Corrected the description of legacy interrupts for multi-function configurations. The app_int_sts_vec[7:0] bus controls generation TLP messages for legacy interrupts.
  • Revised discussion of Application Layer Interrupt Handler Module to include legacy interrupt generation.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Cores table. Out-of-order Completions are not supported transparently for the Avalon-MM with DMA interface.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.
  • Restored Configuration Space Register Access section.
  • Corrected minor errors and typos.
2016.10.31 16.1

Made the following changes to the user guide:

  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Corrected description of tl_cfg* bus. Provided sample RTL code to show how sample tl_cfg_ctl.Corrected tl_cfg_ctl Timing diagram.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
2016.05.02 16.0 Made the following changes:
  • The Quick Start Guide no longer supports the DMA design example.
  • Added figure for TX 3-dword header with qword aligned data.
  • Added statement that the testbench can only simulate a single Endpoint or Root Port at a time.
  • Enhanced statements covering the deficiencies of the Intel-provided testbench.
  • Corrected minor errors and typos.
2015.11.30 15.1 Made the following changes:
  • Added definition of the hip_reconfig_clk in the Hard IP Reconfiguration Signals chapter.
  • Removed the dlup signal which is no longer included in the Hard IP Status interface.
  • Added definition for tx_fifo_empty signal.
  • Corrected the frequency range in the Clock Summary table.
  • Added description of the Altera PCIe Reconfig Driver in the Connecting the Transceiver Reconfiguration Controller IP Core topic.
  • Added a FAQ chapter.
  • Added figure illustrating data alignment for the TX 3-dword header with qword aligned address.
  • Added TLP Support Comparison for all Hard IP for PCI Express IP Cores in Datasheet chapter.
  • Added new topic on Autonomous Mode in which the Hard IP for PCI Express begins operation when the periphery configuration completes.
  • Added SDC Timing Constraints to the Design Implementation chapter.
2014.12.15 14.1 Made the following changes to the user guide:
  • In the figured titled Specifying the Number of Transceiver Interfaces for Arria V and Cyclone V Devices, removed the check mark Calibrate duty cycle during power up. Duty cycle calibration occurs during Gen1 to Gen2 speed changes.
  • Corrected discussion of soft and hard reset controllers. The hardened reset controller is used for Arria V and Cyclone V devices.
  • Added simulation log file, altpcie_monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory. Generation of the log file requires the following simulation file, <install_dir>altera/altera_pcie/altera_pcie_<dev>_hip/altpcie_monitor_<dev>_dlhip_sim.sv, that was not present in earlier releases of the Quartus II software.
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Corrected Channel Utilization table for x1 instances. Data is driven on Channel 0. The CMU clock is on Channel 1.
2014.06.30 14.0

Made the following changes to the Intel® Arria® 10 Hard IP for PCI Express:

  • Increased the size of lmi_addr to 15 bits.

Made the following changes to the user guide:

  • Created separate user guides for variants using the Avalon-MM, Avalon-ST, and Avalon-MM with DMA interfaces to the Application Layer.
  • Added Next Steps in Creating a Design for PCI Express to Datasheet chapter.
  • Enhanced definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Changed the default reset controller settings. By default Gen1 devices use the Hard Reset Controller. Gen2 uses the Soft Reset Controller.
  • Removed references to the MegaWizard® Plug-In Manager. In 14.0 the IP Parameter Editor Powered by Platform Designer has replaced the MegaWizard Plug-In Manager.
  • Removed reference to Gen2 x1 62.5 MHz configuration in Application Layer Clock Frequency for All Combination of Link Width, Data Rate and Application Layer Interface Widths table. This configuration is not supported.
  • Added definition for test_in[6] test_out bus.
  • Added definitions for Hard IP Reconfiguration bus. This bus became an optional feature in version 13.1 of the core.
  • Updated interrupt interface to reflect changes for multi-function support: app_int_sts implements legacy interrupts.
  • Added definitions for the txmargin, txswing, and testin_zero signals.
  • Removed definition for the busy_xcvr_reconfig signal which is not used.
  • Added section on relaxed ordering.
  • Added sections on making analog QSF and pin assignments.
  • Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.
  • Improved description of qword alignment of TLPs.
  • Added fact that DCD calibration is required for Gen2 data rate in the description of the transceiver reconfiguration signals. Updated figure showing Transceiver Reconfiguration Controller parameter editor.
  • Removed references to the ATX PLL. This PLL is not available for Intel® Arria® 10
  • Removed soft reset controller .sdc constraints from the <install_dir>/ip/altera/altera_pcie/altera_pcie_hip_ast_ed/altpcied_<dev>.sdc example. These constraints are now in a separate file in the synthesis/submodules directory.
  • Updated Power Supply Voltage Requirements table.
2014.12.20 13.1 Made the following changes:
  • Added constraints for refclk when CvP is enabled.
  • Corrected location information for nPERSTL*.
  • Corrected definition of test_in[4:1].
  • In Debugging chapter, under changing between soft and hard reset controller, changed the file name in which the parameter hip_hard_reset_hwtclmust be set to 0 to use the soft reset controller.
  • Added explanation of channel labeling for serial data. The Hard IP on the left side of the device must connect to the appropriate channels on the left side of the device, and so on.
  • Corrected connection for the Transceiver Reconfiguration Controller IP Core reset signal, alt_xcvr_reconfig_0 mgmt_rst_reset, Getting Started with the Avalon-MM Arria V Hard IP for PCI Express. This reset input connects to clk_0 clk_reset.
  • Added definition of nreset_status for variants using the Avalon-MM interface.
  • In Transaction Layer Routing Rules and Programming Model for Avalon-MM Root Port , added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number. Application Layer software must filter out requests for device number greater than 0.
  • Added Recommended Reset Sequence to Avoid Link Training Issues to the Debugging chapter.
  • Added limitation for RxmIrq_<n>_i[<m>:0] when interrupts are received on consecutive cycles.
  • Updated timing diagram for tl_cfg_ctl.
  • Removed I/O Read Request and I/O Write Requests from TLPs supported for Avalon-MM interface.
  • Added note that the LTSSM interface can be used for Signal Tap debugging.
  • Added restriction on the use of dynamic transceiver reconfiguration when CvP is enabled.

2014.05.06

13.0

Made the following changes:
  • Timing models are now final.
  • Added instructions for running the Single Dword variant.
  • Corrected definition of test_in[4:1]. This vector must be set to 4’b0100.
  • Corrected connection for mgmt_clk_clk in Figure 3-2.
  • Corrected definition of nPERSTL*. The device has 1 nPERSTL* pin for each instance of the Hard IP for PCI Express in the device.
  • Corrected feature comparison table in Datasheet chapter. The Avalon-MM Hard IP for PCI Express IP Core does not support legacy endpoints.
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