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1. Datasheet
2. Getting Started with the Arria V Hard IP for PCI Express
3. Parameter Settings
4. Interfaces and Signal Descriptions
5. Registers
6. Interrupts
7. Error Handling
8. IP Core Architecture
9. Transaction Layer Protocol (TLP) Details
10. Throughput Optimization
11. Design Implementation
12. Additional Features
13. Hard IP Reconfiguration
14. Transceiver PHY IP Reconfiguration
15. Testbench and Design Example
16. Debugging
A. Transaction Layer Packet (TLP) Header Formats
B. Lane Initialization and Reversal
C. Document Revision History
1.1. Arria V Avalon-ST Interface for PCIe Datasheet
1.2. Features
1.3. Release Information
1.4. Device Family Support
1.5. Configurations
1.6. Example Designs
1.7. Debug Features
1.8. IP Core Verification
1.9. Performance and Resource Utilization
1.10. Recommended Speed Grades
1.11. Creating a Design for PCI Express
4.1. Arria V Hard IP for PCI Express with Avalon-ST Interface to the Application Layer
4.2. Clock Signals
4.3. Reset Signals
4.4. Hard IP Status
4.5. Error Signals
4.6. ECRC Forwarding
4.7. Interrupts for Endpoints
4.8. Interrupts for Root Ports
4.9. Completion Side Band Signals
4.10. Transaction Layer Configuration Space Signals
4.11. LMI Signals
4.12. Power Management Signals
4.13. Physical Layer Interface Signals
5.1. Correspondence between Configuration Space Registers and the PCIe Specification
5.2. Type 0 Configuration Space Registers
5.3. Type 1 Configuration Space Registers
5.4. PCI Express Capability Structures
5.5. Intel-Defined VSEC Registers
5.6. CvP Registers
5.7. Uncorrectable Internal Error Mask Register
5.8. Uncorrectable Internal Error Status Register
5.9. Correctable Internal Error Mask Register
5.10. Correctable Internal Error Status Register
15.6.1. ebfm_barwr Procedure
15.6.2. ebfm_barwr_imm Procedure
15.6.3. ebfm_barrd_wait Procedure
15.6.4. ebfm_barrd_nowt Procedure
15.6.5. ebfm_cfgwr_imm_wait Procedure
15.6.6. ebfm_cfgwr_imm_nowt Procedure
15.6.7. ebfm_cfgrd_wait Procedure
15.6.8. ebfm_cfgrd_nowt Procedure
15.6.9. BFM Configuration Procedures
15.6.10. BFM Shared Memory Access Procedures
15.6.11. BFM Log and Message Procedures
15.6.12. Verilog HDL Formatting Functions
15.7.1. Changing Between Serial and PIPE Simulation
15.7.2. Using the PIPE Interface for Gen1 and Gen2 Variants
15.7.3. Viewing the Important PIPE Interface Signals
15.7.4. Disabling the Scrambler for Gen1 and Gen2 Simulations
15.7.5. Disabling 8B/10B Encoding and Decoding for Gen1 and Gen2 Simulations
15.7.6. Changing between the Hard and Soft Reset Controller
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9.3.1. Using Relaxed Ordering
Transactions from unrelated threads are unlikely to have data dependencies. Consequently, you may be able to use relaxed ordering to improve system performance. The drawback is that only some transactions can be optimized for performance. Complete the following steps to decide whether to enable relaxed ordering in your design:
- Create a system diagram showing all PCI Express and legacy devices.
- Analyze the relationships between the components in your design to identify the following hazards:
- Race conditions: A race condition exists if a read to a location can occur before a previous write to that location completes. The following figure shows a data producer and data consumer on opposite sides of a PCI-to-PCI bridge. The producer writes data to the memory through a PCI-to-PCI bridge. The consumer must read a flag to confirm the producer has written the new data into the memory before reading the data. However, because the PCI-to-PCI bridge includes a write buffer, the flag may indicate that it is safe to read data while the actual data remains in the PCI-to-PCI bridge posted write buffer.
Figure 67. Design Including Legacy PCI Buses Requiring Strong Ordering
- A shared memory architecture where more than one thread accesses the same locations in memory.
If either of these conditions exists, relaxed ordering leads to incorrect results.
- Race conditions: A race condition exists if a read to a location can occur before a previous write to that location completes. The following figure shows a data producer and data consumer on opposite sides of a PCI-to-PCI bridge. The producer writes data to the memory through a PCI-to-PCI bridge. The consumer must read a flag to confirm the producer has written the new data into the memory before reading the data. However, because the PCI-to-PCI bridge includes a write buffer, the flag may indicate that it is safe to read data while the actual data remains in the PCI-to-PCI bridge posted write buffer.
- If your analysis determines that relaxed ordering does not lead to possible race conditions or read or write hazards, you can enable relaxed ordering by setting the RO bit in the TLP header.
- The following figure shows two PCIe Endpoints and Legacy Endpoint connected to a switch. The three PCIe Endpoints are not likely to have data dependencies. Consequently, it would be safe to set the relaxed ordering bit for devices connected to the switch. In this system, if relax ordering is not enabled, a memory read to the legacy Endpoint is blocked. The legacy Endpoint read is blocked because an earlier posted write cannot be completed as the write buffer is full. .
Figure 68. PCI Express Design Using Relaxed Ordering
- If your analysis indicates that you can enable relaxed ordering, simulate your system with and without relaxed ordering enabled. Compare the results and performance.
- If relaxed ordering improves performance without introducing errors, you can enable it in your system.