AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.9. Reference Design Files

Table 10.  Reference Design Files List
Type File/Folder Description
IP files

Contains the IP files for the Intel® Arria® 10 External Memory Interfaces IP core, Intel® Arria® 10 Hard IP for PCI Express* IP core, and devkit pins.

Contains the IP file for the Intel® Arria® 10 Partial Reconfiguration Controller IP core, system description ROM, calibration I/O, and all the interface components.

Contains the freeze bridges, the region controller, and the JTAG SLD agent.

Contains all the IP files for the register file system, that is common across all personas.

Contains the JTAG SLD host for the PR region signal tapping. These files are applicable to all the personas.

Contains the JTAG SLD agent for the PR region signal tapping. These files are applicable to the static region.

Contains the IP files for the EMIF logic inside the PR persona.

Platform Designer System Files
Contains the following three Platform Designer subsystems:
  • bsp_top.qsys—top-level subsystem, containing the PCIe* IP core and the External Memory Interfaces IP core.
  • design_top.qsys—static region, encompassing all the Avalon memory mapped interface logic, reset logic, and PR Region Controller IP core.
  • pr_subsystem.qsys—contains all the logic to communicate and interact with the PR region.
SystemVerilog design files

Contains the top-level wrapper. Also contains the SystemVerilog description for generic components in the three subsystems, and the PR region wrapper.

Contains all the source files for the basic DSP persona.

Contains all the source files for the basic arithmetic persona.

Contains all the source files for the DDR4 access persona.

Contains all the source files for the Game of Life persona.

Contains all the source files for the parent persona.

Example personas that use the template for persona configuration. These examples demonstrate integrating a custom persona RTL into the reference design.

Memory files

Used for system description ROM.
Synopsys Design Constraints Files

Synthesis constraints for the design.

Provides exceptions.

Auto-generated constraints from pcie_subsystem_alt_pr.ip file.

Intel® Quartus® Prime Project File

Contains all the revisions.
Intel® Quartus® Prime Settings Files

Base revision settings file for single DDR4 access persona.

Implementation revision settings file for the parent persona with two DDR4 access personas.

Implementation revision settings file for the parent persona with two basic DSP personas.

Implementation revision settings file for the parent persona with two basic arithmetic personas.

Implementation revision settings file for the parent persona with two Game of Life personas.

Implementation revision settings file for a single DDR4 access persona without the parent persona.

Implementation revision settings file for a single basic arithmetic persona without the parent persona.

Implementation revision settings file for a single Game of Life persona without the parent persona.

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