AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
Public
Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.4.1.3.5. Partial Reconfiguration Logic

The reference design provides the following personas:

Table 5.  Reference Design Personas
Persona Description
DDR4 access

Performs a sweep across a memory span, first writing, and then reading each address.

Basic DSP

Provides access to a 27x27 DSP multiplier and demonstrates hardware acceleration.

Basic arithmetic

Includes a basic 32-bit unsigned adder and demonstrates hardware acceleration.

Game of Life

Includes an 8x8 Conway's Game of Life and demonstrates hardware acceleration.

Parent persona

A wrapper that instantiates two child partitions. The parent persona also connects the two child personas to the static region with their own PR region controller, BAR freeze bridge, and DDR4 freeze bridge.

Each persona has an 8-bit persona_id field in the pr_data register to indicate a unique identification number. A 32-bit control register and 16 I/O registers follow the 8-bit persona_id. The 16 I/O registers are 32-bit each, with 8 bits for device inputs, and 8 bits for device outputs. Each persona uses these registers in different ways. For more information, refer to the source code for each of the personas.

Additionally, the reference design provides a template to implement your custom persona. This template persona allows you modify the RTL, create a wrapper to interface with the register file, compile, and run your design.

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