AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.7.3.2. Programming the Design Using Example Applications

The following steps describe programming your design using the provided scripts:

  1. Program the base revision .sof file using the programmer. Power cycle the host PC to allow the PCIe* link to enumerate. To ensure that the FPGA appears as a PCIe* device, type the following from the Linux shell: 
    lspci -vvvd1172:
  2. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio
  3. To replace the parent PR partition in the design with any of the following single function PR persona, type the following from the Linux shell: 
    fpga-configure -p <rbf file from list> 10000
    where <rbf file from list> is one of the following files:
    • a10_pcie_devkit_cvp_normal_basic_arithmetic.pr_partition
    • a10_pcie_devkit_cvp_normal_basic_dsp.pr_partition
    • a10_pcie_devkit_cvp_normal_ddr4_access.pr_partition
    • a10_pcie_devkit_cvp_normal_gol.pr_partition
  4. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio
  5. To program a parent PR partition that contains two child partitions, type the following from the Linux shell: 
    fpga-configure -p a10_pcie_devkit_cvp_ddr4_access.pr_partition.rbf 10000
    Both child partitions are DDR4 access personas.
  6. To verify the functionality of the design, type the following from the Linux shell: 
    ./example_host_uio
  7. Further, you can reprogram each of the child PR partitions with any combination of personas. The following files generate in the output_files directory:
    • a10_pcie_devkit_cvp_ddr4_access.pr_partition.pr_child_partition_1.rbf
    • a10_pcie_devkit_cvp_basic_dsp.pr_partition.pr_child_partition_0.rbf
    • a10_pcie_devkit_cvp_basic_dsp.pr_partition.pr_child_partition_1.rbf
    • a10_pcie_devkit_cvp_basic_arithmetic.pr_partition.pr_child_partition_0.rbf
    • a10_pcie_devkit_cvp_basic_arithmetic.pr_partition.pr_child_partition_1.rbf
    • a10_pcie_devkit_cvp_gol.pr_partition.pr_child_partition_0.rbf
    • a10_pcie_devkit_cvp_gol.pr_partition.pr_child_partition_1.rbf
    Each bitstream file is unique to the particular child PR region, and not interchangeable. For example, *.pr_child_partition_0.rbf file is only compatible with child PR region 0, and not 1.
  8. To program each child region, type the following in the Linux shell:
    For child region 0: 
    fpga-configure -p <persona>.pr_partition.pr_child_partition_0.rbf 10
    For child region 1: 
    fpga-configure -p <persona>.pr_partition.pr_child_partition_1.rbf 20

    The PR region controller for the larger parent PR region is at address 0x10000. The PR region controller for the two smaller child PR regions is at addresses 0x10 and 0x20 respectively.

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