AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.7.2. fpga-configure

Use the fpga-configure utility to perform partial reconfiguration. The script accepts a .rbf file for a given persona. The script performs the following functions:
  • Communicates with the driver to remove device sub-drivers, if any
  • Communicates with the fpga-region-controller script to assert/de-assert freeze
  • Writes the .rbf to the Partial Reconfiguration Controller IP core
  • Re-deploys the sub-drivers, if any, that are required upon successful PR
To perform PR over PCIe* , run the following command: 
fpga-configure -p <path-to-rbf> <region_controller_addr>
Table 8.   fpga-configure Command-Line Options
Option Description
-p

Performs partial reconfiguration over PCIe* programming.

-d

Disables the advanced error reporting on the PCIe* link. Advanced error reporting generally reports any critical errors along the PCIe* link, directly to the kernel. If the PCIe* link is completely disabled, the kernel responds by crashing the system. You must disable advanced error reporting during full chip configuration, as full chip configuration brings down the PCIe* link.

-e

Enables the advanced error reporting for the PCIe* link. Use this option after full chip configuration to ensure the integrity of the PCIe* link.

-r

Prints the contents of a debug ROM within the reference design. Use for debug purposes.

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