AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.6. Bringing Up the Reference Design

The reference design is available in the following location:

https://github.com/intel/fpga-partial-reconfig

To access the reference design, navigate to the ref_designs sub-folder. Copy the a10_pcie_devkit_cvp_hpr folder to the home directory in your Linux system.

To bring up the reference design on the board:
  1. Plug-in the Intel® Arria® 10 GX FPGA development board to an available PCIe* slot in your host machine.
  2. Connect the host machine's ATX auxiliary power connector to the 12 V ATX input J4 of the development board.
  3. Power-up the host machine.
  4. Verify the micro-USB cable connection to the FPGA development board. Ensure that no other applications that use the JTAG chain are running.
  5. Navigate to the a10_pcie_devkit_cvp_hpr/software/installation folder in your system.
  6. To overwrite the existing factory image on the board with the reference design, execute the flash.pl script.
  7. Pass the JTAG cable number of your connected device as an argument to the script (for example, perl flash.pl 1).
    Running this script configures the device with the contents of the flash.pof file. This parallel object file comes directly from the a10_pcie_devkit_cvp.sof file present in the project directory. The flash.pof file acts as the base image for the reference design.
    Note: Ensure successful compilation of the design before running this script.
  8. Power-cycle the host machine.
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