AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.1.2. Memory Address Mapping

The Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP connects to the design core through two Avalon® memory mapped master interfaces. These Avalon® memory mapped master interfaces are base address registers (BARs), BAR 2 and BAR 4. BAR 2 connects the PR driver to the following components:

  • The Partial Reconfiguration Controller Intel® Arria® 10/Cyclone 10 GX FPGA IP
  • The system description ROM

The BAR 4 Avalon® memory map connects to the following components:

  • The freeze bridges
  • The Partial Reconfiguration Region Controller Intel® FPGA IP
  • Up to 8 kilobytes (KB) of memory in the PR region

The following table lists the memory address mapping for the Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP:

Table 1.  Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP Memory Address Map
Domain Address Map Base End
BAR 2 System Description ROM 0x0000_0000 0x0000_0FFF
BAR 2 PR IP 0x0000_1000 0x0000_103F
BAR 4 PR Region 0x0000_0000 0x0000_FFFF
BAR 4 PR Region Controller 0x0001_0000 0x0001_000F
BAR 4 DDR4 Calibration Export 0x0001_0010 0x0001_001F

The External Memory Interfaces Intel® Arria® 10 FPGA IP provides status on DDR4 calibration. During initialization, the External Memory Interfaces Intel® Arria® 10 FPGA IP performs training to reset the DDR4 interface. The EMIF calibration flag reports the training success or the failure to the host. The host takes the necessary action in the event of a DDR4 training failure.

The following table lists the memory address mapping from the External Memory Interfaces Intel® Arria® 10 FPGA IP to the PR logic:

Table 2.  External Memory Interfaces Intel® Arria® 10 FPGA IP Address Map
Address Map Base End
DDR 0x0000_0000 0x7fff_ffff

The PR logic accesses the 2 gigabyte (GB) DDR4 memory space using an Avalon® memory mapped master interface.

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