AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design: for Intel® Arria® 10 Devices

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ID 683730
Date 1/20/2021
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Document Table of Contents
Document Table of Contents x
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices x
1.1. Reference Design Overview 1.2. Floorplanning 1.3. Getting Started 1.4. Reference Design Components 1.5. Compiling the Reference Design 1.6. Bringing Up the Reference Design 1.7. Testing the Reference Design 1.8. Extending the Reference Design with Custom Persona 1.9. Reference Design Files 1.10. Document Revision History for AN 813: Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices
1.1. Reference Design Overview x
1.1.1. Clocking Scheme 1.1.2. Memory Address Mapping
1.3. Getting Started x
1.3.1. Hardware and Software Requirements 1.3.2. Installing the Intel® Arria® 10 GX FPGA Development Kit 1.3.3. Installing the Linux Driver
1.4. Reference Design Components x
1.4.1. BSP Top
1.4.1. BSP Top x
1.4.1.1. Intel Arria 10/Cyclone 10 Hard IP for PCI Express IP 1.4.1.2. External Memory Interfaces Intel® Arria® 10 FPGA IP 1.4.1.3. Design Top
1.4.1.3. Design Top x
1.4.1.3.1. Global Reset Logic 1.4.1.3.2. PR Region Wrapper 1.4.1.3.3. Parent PR Region 1.4.1.3.4. Partial Reconfiguration Region Controller Intel® FPGA IP 1.4.1.3.5. Partial Reconfiguration Logic
1.7. Testing the Reference Design x
1.7.1. program_fpga_jtag 1.7.2. fpga-configure example_host_uio
example_host_uio x
1.7.3.1. Compiling the Example Applications 1.7.3.2. Programming the Design Using Example Applications
1. Hierarchical Partial Reconfiguration over PCI Express* Reference Design for Intel® Arria® 10 Devices

1.5. Compiling the Reference Design

  1. Ensure that the project's a10_pcie_devkit_cvp.qsf file includes the following assignment: 
    set_instance_assignment -name EXPORT_PARTITION_SNAPSHOT_FINAL 
   a10_pcie_devkit_cvp_static.qdb -to \
   u_top|design_core|pr_region_wrapper|pr_persona_wrapper|u_pr_logic \
   -entity a10_pcie_ref_design
  2. To compile the base revision of the reference design, run the following command from the project directory level: 
    quartus_sh --flow compile a10_pcie_devkit_cvp -c a10_pcie_devkit_cvp
    All the implementation revisions except the base revision contain the following QDB file partition assignment in their respective .qsf files: 
    set_instance_assignment -name QDB_FILE_PARTITION \
      a10_pcie_devkit_cvp_static.qdb -to |
    This assignment imports the .qdb file representing the reference design static region logic into the subsequent PR persona implementation compile. Each implementation revision also contains one or two ENTITY_REBINDING assignment. This assignment links the hierarchy of the static region and the hierarchy of the PR persona. For example, a10_pcie_devkit_cvp_ddr4_access.qsf contains the following entity rebinding assignment: 
    set_instance_assignment -name ENTITY_REBINDING \
      parent_persona_top -to \
      u_top|design_core|pr_region_wrapper|pr_persona_wrapper|u_pr_logic
    For more information, please refer to the Partial Reconfiguration Design Flow section in the Partial Reconfiguration User Guide.
  3. To compile all the non-HPR personas, run the following commands: 
    quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_normal_ddr4_access
quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_normal_basic_arithmetic
quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_normal_basic_dsp
quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_normal_gol
  4. Ensure that this revision defines the child Logic Lock region with the same settings as the base revision.
  5. To compile the HPR parent persona, run the following command: 
    quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_ddr4_access
  6. Export the parent PR partition's .qdb file by clicking Project > Export Design Partition. Specify the following options for the partition:
    Table 6.  Parent PR Partition Option Values
    Option Value
    Partition name pr_partition
    Partition database file <project>/a10_pcie_devkit_cvp_ddr4_access_pr_partition_final.qdb
    Include entity-bound SDC files Disable
    Snapshot Final
    All the HPR child implementation revisions contain an additional QDB FILE PARTITION assignment: 
    set_instance_assignment -name QDB_FILE_PARTITION \
    a10_pcie_devkit_cvp_ddr4_access_pr_partition_final.qdb -to \
    u_top|design_core|pr_region_wrapper|pr_persona_wrapper|u_pr_logic
    This assignment imports the .qdb file representing the HPR parent region into the subsequent HPR child region compilation. Because the HPR child revisions comprise of two child regions, they contain two ENTITY REBINDING assignments. 
    set_instance_assignment -name ENTITY_REBINDING \
    basic_arithmetic_persona_top -to \
    u_top|design_core|pr_region_wrapper| \
    pr_persona_wrapper|u_pr_logic|u0|child_region_0|u_child_pr_logic
 
set_instance_assignment -name ENTITY_REBINDING \
    basic_arithmetic_persona_top -to \
    u_top|design_core|pr_region_wrapper|pr_persona_wrapper| \
    u_pr_logic|u0|child_region_1|u_child_pr_logic
  7. To compile the HPR child personas, run the following commands: 
    quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_basic_arithmetic
quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_basic_dsp
quartus_sh --flow compile a10_pcie_devkit_cvp -c \
      a10_pcie_devkit_cvp_gol
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