PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 8/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series 3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series 4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces 2.2.2. Dynamic Reconfiguration
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.1.1. Clocks x
2.2.1.1.1. Clock Frequency Relationships
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions
2.5. Design Example x
2.5.1. Generate the Design Example 2.5.2. Verify Simulation Design Examples using Tester IP
2.5.1. Generate the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Dynamic Reconfiguration Design Examples
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generate the Synthesis Design Example 2.5.1.1.2. Generate the Simulation Design Example
2.5.1.2. Dynamic Reconfiguration Design Examples x
2.5.1.2.1. Generate the Synthesis Design Example 2.5.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects 3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree 3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces 3.2.4. Dynamic Reconfiguration 3.2.5. I/O Timing
3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces x
3.2.3.1. Clocks 3.2.3.2. Output Path 3.2.3.3. Input Path
3.2.3.1. Clocks x
3.2.3.1.1. Clock Frequency Relationships
3.2.4. Dynamic Reconfiguration x
3.2.4.1. Connectivity 3.2.4.2. Reconfiguration Features and Register Addressing 3.2.4.3. Dynamic Reconfiguration Guidelines
3.2.4.2. Reconfiguration Features and Register Addressing x
3.2.4.2.1. Control Registers Addresses 3.2.4.2.2. Control Registers
3.2.4.3. Dynamic Reconfiguration Guidelines x
3.2.4.3.1. Strobe Enable Window Calibration 3.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 3.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset
3.6. Design Example x
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generate the Synthesis Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Generate the Synthesis Design Example 3.6.1.2.2. Generate the Simulation Design Example
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example 5.7. Application Specific Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generate the Design Example
5.6.1. Generate the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generate the Hardware Design Example 5.6.1.1.2. Generate the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration with Debug Kit 5.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
5.7. Application Specific Design Example x
5.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

3.3.2.3. Input Path Signals

Table 38.  Input Path SignalsInput path signals are signals that are available when you set the Pin Type parameter to Input or Bidirectional. The <n> in the signal names below represents the group number in the IP.
Signal Name Direction Width Description
group_<n>_data_to_core Output

Quarter-rate DDR: 8 x PIN_WIDTH

Quarter-rate SDR: 4 x PIN_WIDTH

Output data to the core logic. Valid on group_<n>_rdata_valid. Synchronous to the core_clk_out output from the IP.
group_rdata_en Input

Quarter-rate: 4

This signal represents the number of expected words to read from the external device.

This signal is set to high after a read command is issued. Synchronous to the core_clk_out output from the IP.

When using the IP as a receiver, assert this signal after interface_locked signal is asserted and group_strobe_in is stable.

This signal is shared across all groups.

group_<n>_rdata_valid Output

Quarter-rate: 4

This signal determines which data are valid when reading from Read FIFO. Delayed by READ_LATENCY with margin and aligned to the core clock rate. For example, in quarter-rate, the delay is a multiple of 4 external clock cycles.

Synchronous to the core_clk_out output from the IP.

group_<n>_data_in/

group_<n>_data_io

Input/Bidirectional

1 to 34

Input and output data from/to external device. Synchronous to the group_<n>_strobe_in or group_<n>_strobe_io input. The first data_in must be associated with positive edge of group_<n>_strobe_in/group_<n>_strobe_io.

If the pin type is set to Input, the group_<n>_data_in ports are used. If the pin type is set to bidirectional, the group_<n>_data_io ports are used.

group_<n>_strobe_in/ group_<n>_strobe_io Input/Bidirectional 1

Input and output strobe from/to external device. If the pin type is set to Input, the group_<n>_strobe_in signal is used. If the pin type is set to Bidirectional, the group_<n>_strobe_io signal is used.

group_<n>_strobe_in_n/group_<n>_strobe_io_n Input/Bidirectional 1 Negative strobe from/to external device. This is used if the Strobe Configuration parameter is set to Differential. If the pin type is set to Input, the group_<n>_strobe_in_n signal is used. If the pin type is set to Bidirectional, the group_<n>_strobe_io_n signal is used.
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