PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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2.2.2. Dynamic Reconfiguration

Enabling dynamic reconfiguration exposes an Avalon® memory-mapped interface that can be used for reconfiguring input and output delays in the PHY to perform calibration. The calibration goal is to configure the delay settings to maximize the capture window. Access to the Avalon® memory-mapped interface should be performed via Calibration IP, which provides an ARM AMBA* AXI4 Lite Interface. Calibration IP can be connected to two PHY Lite for Parallel Interfaces instances in an IO bank.

For differential data, the output delay settings should be programmed for both pins in a differential pair. The input settings, however, should be programmed only for the even pin.

Reset of the PHY can only be achieved by enabling dynamic reconfiguration and writing to the TrainReset bit. The reset port in PHY Lite for Parallel Interfaces IP is only for power-up reset.

Figure 9. Connection of Calibration IP to PHY Lite for Parallel Interfaces IPThis figure shows the connection of Calibration IP to PHY Lite for Parallel Interfaces IP.