PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

ID 683716
Date 8/02/2023
Public

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2.2.2.2. Dynamic Reconfigurable Delays

The following table lists delays that can only be reconfigured when the corresponding read/write path is not being used:

Table 12.  Dynamic Reconfigurable Delays
Configurable Settings Width Description Unit Granularity
TxDqDelay 11 Output delay for data and strobe 1/128 of VCO cycle per pin
RxDqsNDelayPi 7 Phase shift in negative edge of DQS 1/128 of VCO cycle per pin
RxDqsPDelayPi 7 Phase shift in positive edge of DQS 1/128 of VCO cycle per pin
RxRcvEnPiRank0 11 RcvEn delay 1/128 of VCO cycle per nibble
DqsSenseAmpDelay 5 DQS sense amplifier delay PHY clock cycle per nibble
DqSenseAmpDuration 4 DQ sense amplifier duration PHY clock cycle per nibble
DqSenseAmpDelay 5 DQ sense amplifier delay PHY clock cycle per nibble
DqOdtDuration 4 DQ ODT duration PHY clock cycle per nibble
DqOdtDelay 5 DQ ODT delay PHY clock cycle per nibble
DqsOdtDuration 4 DQS ODT duration PHY clock cycle per nibble
DqsOdtDelay 5 DQS ODT delay PHY clock cycle per nibble
read_enable_offset 4 Delay before reading from the RX FIFO PHY clock cycle per lane
RxDataVrefL 9 I/O reference voltage lower nibble 1/512 of VCCN per nibble
RxDataVrefU 9 I/O reference voltage upper nibble 1/512 of VCCN per nibble
TrainReset 1 Train reset to clear non-permanent states - self clearing per lane
RLTrainingMode 1 Enables read leveling training mode per lane
DataTrainFeedback_N0 12 Provides feedback for different training steps. In RL Training mode it is simply a counter. per nibble