PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide

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Date 8/02/2023
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Document Table of Contents
Document Table of Contents x
1. About the PHY Lite for Parallel Interfaces IP 2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series 3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series 4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP 5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs 6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives 7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide
1. About the PHY Lite for Parallel Interfaces IP x
1.1. Device Family Support 1.2. Features
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series x
2.1. Release Information 2.2. Functional Description 2.3. Getting Started 2.4. I/O Standards 2.5. Design Example
2.2. Functional Description x
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces 2.2.2. Dynamic Reconfiguration
2.2.1. PHY Lite for Parallel Interfaces Intel Agilex® 7 FPGA IP Top Level Interfaces x
2.2.1.1. Clocks 2.2.1.2. Output Path 2.2.1.3. Input Path
2.2.1.1. Clocks x
2.2.1.1.1. Clock Frequency Relationships
2.2.2. Dynamic Reconfiguration x
2.2.2.1. Calibration IP 2.2.2.2. Dynamic Reconfigurable Delays 2.2.2.3. Register Map
2.3. Getting Started x
2.3.1. Parameter Settings 2.3.2. Signals
2.3.2. Signals x
2.3.2.1. Clock and Reset Interface Signals 2.3.2.2. Output Path Signals 2.3.2.3. Input Path Signals
2.4. I/O Standards x
2.4.1. Design Guidelines
2.4.1. Design Guidelines x
2.4.1.1. DQS Trees 2.4.1.2. Pin Placement Restrictions
2.5. Design Example x
2.5.1. Generate the Design Example 2.5.2. Verify Simulation Design Examples using Tester IP
2.5.1. Generate the Design Example x
2.5.1.1. Design Example without Dynamic Reconfiguration 2.5.1.2. Dynamic Reconfiguration Design Examples
2.5.1.1. Design Example without Dynamic Reconfiguration x
2.5.1.1.1. Generate the Synthesis Design Example 2.5.1.1.2. Generate the Simulation Design Example
2.5.1.2. Dynamic Reconfiguration Design Examples x
2.5.1.2.1. Generate the Synthesis Design Example 2.5.1.2.2. Generate the Simulation Design Example
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series x
3.1. Release Information 3.2. Functional Description 3.3. Getting Started 3.4. I/O Standards 3.5. Design Guidelines 3.6. Design Example
3.2. Functional Description x
3.2.1. Intel Agilex® 7 F-Series and I-Series I/O Sub-bank Interconnects 3.2.2. Intel Agilex® 7 F-Series and I-Series Input DQS/Strobe Tree 3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces 3.2.4. Dynamic Reconfiguration 3.2.5. I/O Timing
3.2.3. PHY Lite for Parallel Interfaces Intel Agilex® 7 for F-Series and I-Series FPGA IP Top Level Interfaces x
3.2.3.1. Clocks 3.2.3.2. Output Path 3.2.3.3. Input Path
3.2.3.1. Clocks x
3.2.3.1.1. Clock Frequency Relationships
3.2.4. Dynamic Reconfiguration x
3.2.4.1. Connectivity 3.2.4.2. Reconfiguration Features and Register Addressing 3.2.4.3. Dynamic Reconfiguration Guidelines
3.2.4.2. Reconfiguration Features and Register Addressing x
3.2.4.2.1. Control Registers Addresses 3.2.4.2.2. Control Registers
3.2.4.3. Dynamic Reconfiguration Guidelines x
3.2.4.3.1. Strobe Enable Window Calibration 3.2.4.3.2. Output and Strobe Enable Minimum and Maximum Phase Settings 3.2.4.3.3. Input DQ/DQS Delay Chains Maximum Values
3.3. Getting Started x
3.3.1. Parameter Settings 3.3.2. Signals
3.3.1. Parameter Settings x
3.3.1.1. Read Latency 3.3.1.2. Write Latency
3.3.2. Signals x
3.3.2.1. Clock and Reset Interface Signals 3.3.2.2. Output Path Signals 3.3.2.3. Input Path Signals
3.4. I/O Standards x
3.4.1. Input Buffer Reference Voltage (VREF) 3.4.2. On-Chip Termination (OCT)
3.4.2. On-Chip Termination (OCT) x
3.4.2.1. RZQ_GROUP Assignment
3.5. Design Guidelines x
3.5.1. Guidelines: Group Pin Placement 3.5.2. Reference Clock 3.5.3. Reset
3.6. Design Example x
3.6.1. Generate the Design Example
3.6.1. Generate the Design Example x
3.6.1.1. Design Example without Dynamic Reconfiguration 3.6.1.2. Dynamic Reconfiguration Design Examples
3.6.1.1. Design Example without Dynamic Reconfiguration x
3.6.1.1.1. Generate the Synthesis Design Example 3.6.1.1.2. Generate the Simulation Design Example
3.6.1.2. Dynamic Reconfiguration Design Examples x
3.6.1.2.1. Generate the Synthesis Design Example 3.6.1.2.2. Generate the Simulation Design Example
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP x
4.1. Release Information 4.2. Functional Description 4.3. Getting Started 4.4. I/O Standards 4.5. Design Guidelines 4.6. Design Example
4.2. Functional Description x
4.2.1. Top Level Interfaces 4.2.2. Clocks 4.2.3. Output Path 4.2.4. Input Path 4.2.5. Dynamic Reconfiguration
4.2.2. Clocks x
4.2.2.1. Clock Frequency Relationships
4.2.3. Output Path x
4.2.3.1. Output Path Data Alignment
4.2.4. Input Path x
4.2.4.1. Input Path Data Alignment
4.2.5. Dynamic Reconfiguration x
4.2.5.1. RTL Connectivity 4.2.5.2. Address Lookup 4.2.5.3. Reconfiguration Features and Register Addressing 4.2.5.4. Calibration Guidelines
4.2.5.1. RTL Connectivity x
4.2.5.1.1. Daisy Chain
4.2.5.2. Address Lookup x
4.2.5.2.1. Strobes 4.2.5.2.2. Parameter Table Examples
4.2.5.3. Reconfiguration Features and Register Addressing x
4.2.5.3.1. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP Control Registers Addresses 4.2.5.3.2. Control Registers Description
4.2.5.4. Calibration Guidelines x
4.2.5.4.1. Strobe Enable Window Calibration 4.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
4.3. Getting Started x
4.3.1. Parameter Settings 4.3.2. Signals
4.3.1. Parameter Settings x
4.3.1.1. Read Latency 4.3.1.2. Write Latency
4.3.2. Signals x
4.3.2.1. Clock and Reset Interface Signals 4.3.2.2. Output Path Signals 4.3.2.3. Input Path Signals 4.3.2.4. Avalon Configuration Bus Interface Signals 4.3.2.5. Termination Signals
4.4. I/O Standards x
4.4.1. Input Buffer Reference Voltage (VREF) 4.4.2. On-Chip Termination (OCT)
4.4.1. Input Buffer Reference Voltage (VREF) x
4.4.1.1. Calibrated VREF Settings
4.4.2. On-Chip Termination (OCT) x
4.4.2.1. RZQ_GROUP Assignment 4.4.2.2. Manual Insertion of OCT Block
4.5. Design Guidelines x
4.5.1. Guidelines: Group Pin Placement 4.5.2. Reference Clock 4.5.3. Reset 4.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 4.5.5. Dynamic Reconfiguration 4.5.6. Timing
4.5.6. Timing x
4.5.6.1. Timing Components 4.5.6.2. Timing Constraints and Files 4.5.6.3. Timing Analysis 4.5.6.4. Timing Closure Guidelines
4.5.6.2. Timing Constraints and Files x
4.5.6.2.1. <variation_name>.sdc 4.5.6.2.2. <variation_name>_parameter.tcl 4.5.6.2.3. <variation_name>_ip_parameters.tcl 4.5.6.2.4. <variation_name>_pin_map.tcl 4.5.6.2.5. <variation_name>_report_timing.tcl 4.5.6.2.6. <variation_name>_report_timing_core.tcl
4.5.6.4. Timing Closure Guidelines x
4.5.6.4.1. Timing Closure: Dynamic Reconfiguration 4.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 4.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 4.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 4.5.6.4.5. I/O Timing Violation 4.5.6.4.6. Internal FPGA Path Timing Violation
4.6. Design Example x
4.6.1. Generate the Design Example
4.6.1. Generate the Design Example x
4.6.1.1. Design Example without Dynamic Reconfiguration 4.6.1.2. Dynamic Reconfiguration Design Examples
4.6.1.1. Design Example without Dynamic Reconfiguration x
4.6.1.1.1. Generate the Hardware Design Example 4.6.1.1.2. Generate the Simulation Design Example
4.6.1.2. Dynamic Reconfiguration Design Examples x
4.6.1.2.1. Dynamic Reconfiguration Using Finite State Machine
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs x
5.1. Release Information 5.2. Functional Description 5.3. Getting Started 5.4. I/O Standards 5.5. Design Guidelines 5.6. Design Example 5.7. Application Specific Design Example
5.2. Functional Description x
5.2.1. Top Level Interfaces 5.2.2. Clocks 5.2.3. Output Path 5.2.4. Input Path 5.2.5. Dynamic Reconfiguration
5.2.2. Clocks x
5.2.2.1. Clock Frequency Relationships
5.2.3. Output Path x
5.2.3.1. Output Path Data Alignment
5.2.4. Input Path x
5.2.4.1. Input Path Data Alignment
5.2.5. Dynamic Reconfiguration x
5.2.5.1. RTL Connectivity 5.2.5.2. Address Lookup 5.2.5.3. Reconfiguration Features and Register Addressing 5.2.5.4. Calibration Guidelines
5.2.5.1. RTL Connectivity x
5.2.5.1.1. Daisy Chain
5.2.5.2. Address Lookup x
5.2.5.2.1. Strobes 5.2.5.2.2. Parameter Table Examples
5.2.5.3. Reconfiguration Features and Register Addressing x
5.2.5.3.1. PHY Lite for Parallel Interfaces Intel Arria 10 FPGA IP and PHY Lite for Parallel Interfaces Intel Cyclone 10 GX IPs Address Registers 5.2.5.3.2. Control Registers Description
5.2.5.4. Calibration Guidelines x
5.2.5.4.1. Strobe Enable Window Calibration 5.2.5.4.2. Output and Strobe Enable Minimum and Maximum Phase Settings
5.3. Getting Started x
5.3.1. Parameter Settings 5.3.2. Signals
5.3.1. Parameter Settings x
5.3.1.1. Read Latency 5.3.1.2. Write Latency
5.3.2. Signals x
5.3.2.1. Clock and Reset Interface Signals 5.3.2.2. Output Path Signals 5.3.2.3. Input Path Signals 5.3.2.4. Avalon Configuration Bus Interface Signals 5.3.2.5. Termination Signals
5.4. I/O Standards x
5.4.1. Input Buffer Reference Voltage (VREF) 5.4.2. On-Chip Termination (OCT)
5.4.1. Input Buffer Reference Voltage (VREF) x
5.4.1.1. Calibrated VREF Settings
5.4.2. On-Chip Termination (OCT) x
5.4.2.1. RZQ_GROUP Assignment 5.4.2.2. Manual Insertion of OCT Block
5.5. Design Guidelines x
5.5.1. Guidelines: Group Pin Placement 5.5.2. Reference Clock 5.5.3. Reset 5.5.4. Constraining Multiple PHY Lite for Parallel Interfaces to One I/O Bank 5.5.5. Dynamic Reconfiguration 5.5.6. Timing
5.5.6. Timing x
5.5.6.1. Timing Components 5.5.6.2. Timing Constraints and Files 5.5.6.3. Timing Analysis 5.5.6.4. Timing Closure Guidelines
5.5.6.2. Timing Constraints and Files x
5.5.6.2.1. <variation_name>.sdc 5.5.6.2.2. <variation_name>_parameter.tcl 5.5.6.2.3. <variation_name>_ip_parameters.tcl 5.5.6.2.4. <variation_name>_pin_map.tcl 5.5.6.2.5. <variation_name>_report_timing.tcl 5.5.6.2.6. <variation_name>_report_timing_core.tcl
5.5.6.4. Timing Closure Guidelines x
5.5.6.4.1. Timing Closure: Dynamic Reconfiguration 5.5.6.4.2. Timing Closure: Input Strobe Setup and Hold Delay Constraints 5.5.6.4.3. Timing Closure: Output Strobe Setup and Hold Delay Constraints 5.5.6.4.4. Timing Closure: Non Edge-Aligned Input Data 5.5.6.4.5. I/O Timing Violation 5.5.6.4.6. Internal FPGA Path Timing Violation
5.6. Design Example x
5.6.1. Generate the Design Example
5.6.1. Generate the Design Example x
5.6.1.1. Design Example without Dynamic Reconfiguration 5.6.1.2. Dynamic Reconfiguration Design Examples
5.6.1.1. Design Example without Dynamic Reconfiguration x
5.6.1.1.1. Generate the Hardware Design Example 5.6.1.1.2. Generate the Simulation Design Example
5.6.1.2. Dynamic Reconfiguration Design Examples x
5.6.1.2.1. Dynamic Reconfiguration with Debug Kit 5.6.1.2.2. Dynamic Reconfiguration Using Finite State Machine
5.7. Application Specific Design Example x
5.7.1. Implementation using the PHY Lite for Parallel Interfaces IP
1. About the PHY Lite for Parallel Interfaces IP
2. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for M-Series
3. PHY Lite for Parallel Interfaces Intel Agilex 7 FPGA IP for F-Series and I-Series
4. PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP
5. PHY Lite for Parallel Interfaces Intel Arria 10 and Intel Cyclone 10 GX FPGA IPs
6. PHY Lite for Parallel Interfaces Intel® FPGA IP User Guide Document Archives
7. Document Revision History for the PHY Lite for Parallel Interfaces IP User Guide

2.2.1.3. Input Path

The simplified input path of the IP consists of pipeline registers, RX FIFO, shift registers, and phase shift.
Figure 5. Simplified Input PathThe following figure shows the input path for the PHY Lite for Parallel Interfaces IP.
Table 6.  Components in Simplified Input PathThis table lists the components in the simplified input path for the PHY Lite for Parallel Interfaces IP.
Component Description
Pipeline Registers Represent pipeline stages in the input path
2 RX FIFOs

Perform 2:1 rate conversion on the RX data

  • At positive edge of strobe_in signal
  • At negative edge of strobe_in signal
Shift Registers Perform the following functions:
  • Delay the RcvEn signal in VCO cycle increments
  • The read_enable_offset shift register delays the rdata_valid signal
Phase Shifts Perform the following functions:
  • Delay RcvEn signal in 1/128 VCO cycle increments
  • Delay RxDqsNDelayPi/RxDqsPDelayPi signal

There are five types of delay in the input path. The following table describes the delays:

Table 7.  Types of Delay in Input Path
Delay Type Description
Inherent latency Static
  • Captured in pipeline stages from the assertion of rdata_en signal in core until internal signal, RcvEn, is asserted
RcvEn delay (internal signal generated from input signal rdata_en) Dynamic
  • Can be reconfigured in control registers
  • The GUI parameter Additional Receiver Enable Latency is the RcvEn delay and can be programmed both statically from the GUI and dynamically
Positive-edge strobe_in delay Dynamic
Negative-edge strobe_in delay Dynamic
read_enable_offset delay Dynamic
Table 8.  Input path Reconfigurable Delays DescriptionThis table details all the reconfigurable input path delays for the PHY Lite for Parallel Interfaces IP.
Feature Description Bit-field Description Min Max
RxRcvEnPiRank0 [10:7]
  • RcvEn delay
  • There are two RxRcvEnPiRank0 registers per lane. One controls the lower nibble (6 pins) and the other controls the upper nibble of the lane.
  • In PHY Lite IP, the nibbles cannot be used independently. Both control signals must be programmed to the same value.
 Bit 10 to bit 7 represents integer number of VCO clock cycles to delay RcvEn signal. 0 15
RxRcvEnPiRank0 [6:0] Bit 6 to bit 0 represents additional phase shift in RcvEn signal measured in 1/128 of VCO clock period. 0 127

RxDqsNDelayPi

[6:0]
  • strobe­_in delay
  • There are two RxDqsNDelayPi and RxDqsPDelayPi for each pin. Each pin receives a copy of the DQS and can phase-shift each edge of the DQS independently of other pins.
  • Usually both edges should be set to the same delay value, but different values can be used to correct uneven duty cycle.
  • The effective range of this delay setting is up to 1 VCO clock cycle.
 Phase shift in the negative edge of the DQS for each pin measured in 1/128 of VCO clock period. 0 127

RxDqsPDelayPi

[6:0]

 Phase shift in the positive edge of the DQS for each pin measured in 1/128 of VCO clock period. 0 127

read_enable_offset

[3:0]
  • rdata_valid delay
  • An adjustable setting that changes the delay before starting to read from the RX FIFO, effectively delaying the rdata_valid signal.
  • This delay setting is downstream from the integer portion of the RcvEn delay, so any additional RcvEn delay applies to the rdata_valid signal as well.
Delay before reading from the RX FIFO measured in number of PHY clock cycles. 0 15
Figure 6. Input OperationThis figure shows the input operation for the PHY Lite for Parallel Interfaces IP.

The preceding figure shows an example of RX data transfer in QR DDR. The data_to_core for each pin is 8 bits wide. PHY Lite uses DDR4 preamble settings, expecting one cycle of preamble by default. Setting the parameter Capture strobe phase shift to 90 degrees causes PHY Lite IP to accept edge-aligned data.

To ensure that only clock edges associated with valid input data are used, the receiver must be gated off when PHY Lite IP is not accepting any input data. There might be extra toggles or noise on the DQS port, so it is important to use a refined version of the received strobe. The gating signal, RcvEn (receiver enable), is internally derived from rdata_en signal. The RcvEn signal is used to ungate the DQS gate window and can be asserted up to one cycle before the first rising edge of DQS, as shown in the following figure. This means that at most, one cycle preamble is required in the strobe signal.

Figure 7. Ungating DQS Gate WindowThis figure shows ungating of DQS window by internally asserting RcvEn.

The process of shutting off the DQS gate happens automatically once the last burst ends. This is achieved by using two modified versions of the RcvEn signal: RcvEnPiMod and RcvEnPre. RcvEnPiMod is derived from RcvEnPi, which is the output of the serializer. RcvEnPiMod turns on at the same time as RcvEnPi, but the falling edge is adjusted. RcvEnPre starts a burst counter that counts up to burst length / 2 repeatedly. PHY Lite IP uses Burst Length 4 setting, so the burst counter repeatedly counts from 0 to 1. RcvEnPiMod ends one cycle early. When RcvEnPiMod is low and the burst counter reaches its maximum, RcvEnPre is deasserted at the next negative edge of the DQS, therefore shutting off ungating circuit.

Figure 8. Shutting Off the DQS Gate WindowThe following figure shows how disabling RcvEn shuts off the DQS gate.

In the input path, the ODT (on die termination) and SA (sense amplifier) settings should also be programmed when changing RcvEn delay by dynamic reconfiguration. The ODT and SA are gated off in the idle mode to save power. There are two separate enable signals for these settings, which are tapped from the same shift register as RcvEn. If RcvEn delay is reconfigured, the ODT and SA settings must be adjusted as well to make sure everything in the receiver circuitry turns on at the right time. The relevant settings to reconfigure are DqsSenseAmpDelay, DqsSenseAmpDuration, DqSenseAmpDuration, DqSenseAmpDelay, DqOdtDuration, DqOdtDelay, DqsOdtDuration, and DqsOdtDelay. These settings should be adjusted for both upper and lower nibbles in the lane according to the following table:

Table 9.  Settings for DQ/DQS ODT/SA Delays
RxRcvEnPi[10:7]>>Gear4 1 DqsOdtDelay DqOdtDelay Dq/Dqs SenseAmpDelay
0 2 3 3
1 3 4 4
2 4 5 5
3 5 6 6
4 6 7 7
5 7 8 8
6 8 9 9
7 9 10 10

When changing RcvEn coarse delay or RxRcvEnPiRank0[10:7], Intel recommends updating read_enable_offset to avoid receiving misaligned data in the core. The small values of read_enable_offset may result in RX FIFO underflow, and the large values may result in overflow. Refer to the table below for the allowed values of read_enable_offset according to RcvEn coarse delay.

Table 10.  Allowed values for read_enable_offset based on RcvEn coarse delay
RxRcvEnPiRank0[10:7] Allowed values for read_enable_offset
0, 1, 4, 5, 8, 9, 12, 13 3, 5, 7, 9, 11
2, 3, 6, 7, 10, 11, 14, 15 2, 4, 6, 8, 10, 12
Related Information
1 This value is the shifted value of RxRcvEnPi[10:7] and Gear4 value is always 1
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