AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

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ID 683707
Date 10/30/2021
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Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example

diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga.c ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga.c
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga.c	2021-03-15 14:28:16.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga.c	2021-07-28 15:51:41.262757585 +0100
@@ -17,7 +17,7 @@
 int load_fpga_file(char *, char *, unsigned long);
 
 #define EEP_VPD_I2C_ADDR	0x51
-#define EEP_MAC_OFFSET		0x01
+#define EEP_MAC_OFFSET		0x2D
 #define EEP_SERIAL_OFFSET	0x7
 #define SERIAL_LEN		10
 
@@ -50,7 +50,7 @@
 	const void *blob = gd->fdt_blob;
 
 	printf("Reading MAC addresses from EEPROM ...\n");
-	i2c_read(EEP_VPD_I2C_ADDR, EEP_MAC_OFFSET, 1,
+	i2c_read(EEP_VPD_I2C_ADDR, EEP_MAC_OFFSET, 2,
 	         enetaddr, sizeof(enetaddr));
 
 	eth_env_set_enetaddr_by_index("eth", 0, enetaddr);
@@ -169,4 +169,4 @@
 #endif
 	return 0;
 }
-#endif
\ No newline at end of file
+#endif
diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_de_eval_board_defconfig ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_de_eval_board_defconfig
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_de_eval_board_defconfig	2021-03-15 14:28:16.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_de_eval_board_defconfig	2021-07-28 15:51:41.262757585 +0100
@@ -120,8 +120,8 @@
 CONFIG_USE_TINY_PRINTF=y
 # CONFIG_LIB_RAND is not set
 CONFIG_AUTOBOOT_KEYED=y
-CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds. Stop by pressing \"na\"\n"
-CONFIG_AUTOBOOT_STOP_STR="na"
+CONFIG_AUTOBOOT_PROMPT="autoboot in %d seconds. Stop by pressing \"n\"\n"
+CONFIG_AUTOBOOT_STOP_STR="n"
 CONFIG_BOOTDELAY=5
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SYS_NO_FLASH=y
diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_socdk.h ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_socdk.h
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_socdk.h	2021-03-15 14:28:16.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-bsp/u-boot/files/2018.03/de-eval-board/socfpga_cyclone5_socdk.h	2021-07-28 15:51:41.262757585 +0100
@@ -17,7 +17,7 @@
 #define PHYS_SDRAM_1_SIZE              	0x40000000      /* 1GiB on SoCDK */
 
 /* Booting Linux */
-#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTDELAY		5
 #define CONFIG_BOOTFILE			"zImage"
 #define CONFIG_BOOTARGS                	"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND     		"run callscript; run mmcload; run mmcboot"
diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/recovery-rootfs_1.0.0.bb ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/recovery-rootfs_1.0.0.bb
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/recovery-rootfs_1.0.0.bb	2021-03-15 14:28:16.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/recovery-rootfs_1.0.0.bb	2021-07-28 15:51:41.266757555 +0100
@@ -1,7 +1,7 @@
 DESCRIPTION = "A TTTech recovery root filesystem for update"
 
 IMAGE_FEATURES += "ssh-server-openssh"
-IMAGE_FSTYPES = "ext4"
+IMAGE_FSTYPES = "ext4 tar.gz"
 
 IMAGE_INSTALL = "\
     packagegroup-core-boot \
diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/sdcard-image_1.0.0.bb ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/sdcard-image_1.0.0.bb
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/sdcard-image_1.0.0.bb	2021-03-15 15:04:17.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/images/sdcard-image_1.0.0.bb	2021-07-28 15:51:41.266757555 +0100
@@ -68,6 +68,10 @@
     linuxptp \
     devmem2 \
     python-pip \
+    gdbserver \
+    openssh-sftp-server \
+    packagegroup-core-ssh-openssh \
+    rt-tests \
     haveged \
     "
 
diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init/de-eval-board/ttt-ip-init.sh ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init/de-eval-board/ttt-ip-init.sh
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init/de-eval-board/ttt-ip-init.sh	2021-03-15 14:28:16.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init/de-eval-board/ttt-ip-init.sh	2021-07-28 15:51:41.266757555 +0100
@@ -26,16 +26,23 @@
 # Get a MAC address from the EEPROM from a given offset.
 get_mac()
 {
-    ret_mac=0
-    for i in {1..6}; do
-        o=$(($(i2cget -y 0 0x51 $i b)))
-        ret_mac=$(($ret_mac *0x100 +$o))
-    done
-    ret_mac=$(($ret_mac + $1))
+    #ret_mac=0
+    #for i in {1..6}; do
+    #    o=$(($(i2cget -y 0 0x51 $i b)))
+    #    ret_mac=$(($ret_mac *0x100 +$o))
+    #done
+    #ret_mac=$(($ret_mac + $1))
     # hex-print the mac address (12 chars = 6 octets in hex)
     # ... first sed puts ':' after every 2 chars, i.e., after every octet
     # ... second sed removes the last ':' trailing the line
-    printf "%012x" $ret_mac | sed 's/\(.\{2\}\)/\1:/g' | sed 's/:$//'
+    #printf "%012x" $ret_mac | sed 's/\(.\{2\}\)/\1:/g' | sed 's/:$//'
+    ret_mac=""
+    i2cset -y 0 0x51 0 $1 i
+    for i in 0 1 2 3 4 5; do
+    ret_mac=$ret_mac$(i2cget -y 0 0x51 | sed 's/0x/:/')
+    done
+    echo ${ret_mac#:}
+    
 }
 
 # Configure delays.
@@ -61,15 +68,15 @@
 
     echo -n "edgx_mdio-1:00" > /sys/class/net/sw0p2/phy/mdiobus
     echo -n "edgx_mdio-1:01" > /sys/class/net/sw0p3/phy/mdiobus
-    echo -n "edgx_mdio-1:02" > /sys/class/net/sw0p4/phy/mdiobus
-    echo -n "edgx_mdio-1:03" > /sys/class/net/sw0p5/phy/mdiobus
+    #echo -n "edgx_mdio-1:02" > /sys/class/net/sw0p4/phy/mdiobus
+    #echo -n "edgx_mdio-1:03" > /sys/class/net/sw0p5/phy/mdiobus
 
-    ip link set dev sw0p1 address $(get_mac 3)
-    ip link set dev sw0p2 address $(get_mac 4)
-    ip link set dev sw0p3 address $(get_mac 5)
-    ip link set dev sw0p4 address $(get_mac 6)
-    ip link set dev sw0p5 address $(get_mac 7)
-    ip link set dev sw0ep address $(get_mac 0)
+    ip link set dev sw0p1 address $(get_mac 45)
+    ip link set dev sw0p2 address $(get_mac 51)
+    ip link set dev sw0p3 address $(get_mac 57)
+    #ip link set dev sw0p4 address $(get_mac 6)
+    #ip link set dev sw0p5 address $(get_mac 7)
+    ip link set dev sw0ep address $(get_mac 69)
 
     # set default mqprio setup for 3 traffic classes
     tc qdisc add dev sw0ep root mqprio num_tc 3 map 0 0 0 0 1 1 2 2 2 2 2 2 2 2 2 2 hw 1 mode channel
@@ -78,10 +85,10 @@
     tc qdisc replace dev sw0ep parent 8001:3 pfifo
 
     # Marvell 88E1510P - standard latency mode
-    set_delays sw0p2 phydev tx 4032 412 109 rx 1083 220 203
-    set_delays sw0p3 phydev tx 4032 412 109 rx 1083 220 203
-    set_delays sw0p4 phydev tx 4032 412 109 rx 1083 220 203
-    set_delays sw0p5 phydev tx 4032 412 109 rx 1083 220 203
+    set_delays sw0p2 phydev tx 1663 156 92 rx 1140 180 207
+    set_delays sw0p3 phydev tx 1663 156 92 rx 1140 180 207
+    #set_delays sw0p4 phydev tx 4032 412 109 rx 1083 220 203
+    #set_delays sw0p5 phydev tx 4032 412 109 rx 1083 220 203
 }
 
 stop()
@@ -94,7 +101,7 @@
 case "$1" in
     start|restart|force-reload)
 	echo "Configuring FPGA ..."
-        echo "  Hardware S/N: "$(print_serial)
+        #echo "  Hardware S/N: "$(print_serial)
         start
 	;;
     stop)
diff -Naur ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init-ifupdown/de-eval-board/interfaces ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init-ifupdown/de-eval-board/interfaces
--- ./tmp_orig/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init-ifupdown/de-eval-board/interfaces	2021-03-15 14:28:16.000000000 +0000
+++ ./tmp_mod_rt/ip-solutions-ref/meta-local/recipes-ttt-rootfs/init-ifupdown/de-eval-board/interfaces	2021-07-28 15:51:41.266757555 +0100
@@ -10,7 +10,7 @@
 
 auto sw0ep:1
 iface sw0ep:1 inet static
-	address 192.168.0.1
+	address 192.168.1.20
 	netmask 255.255.255.0
 
 auto br0
@@ -20,8 +20,7 @@
 	up ip link set dev sw0p1 master $IFACE up
 	up ip link set dev sw0p2 master $IFACE up
 	up ip link set dev sw0p3 master $IFACE up
-	up ip link set dev sw0p4 master $IFACE up
-	up ip link set dev sw0p5 master $IFACE up
+
 	up ip link set $IFACE type bridge stp_state 1
 	up mstpctl addbridge $IFACE
 	up mstpctl setforcevers $IFACE mstp
diff -Naur ./tmp_orig/poky/meta-tsn-base/recipes-sysrepo/libyang/libyang_1.0.164.bb ./tmp_mod_rt/poky/meta-tsn-base/recipes-sysrepo/libyang/libyang_1.0.164.bb
--- ./tmp_orig/poky/meta-tsn-base/recipes-sysrepo/libyang/libyang_1.0.164.bb	2021-03-15 14:28:29.000000000 +0000
+++ ./tmp_mod_rt/poky/meta-tsn-base/recipes-sysrepo/libyang/libyang_1.0.164.bb	2021-07-28 15:51:40.054766660 +0100
@@ -4,7 +4,7 @@
 LICENSE = "BSD-3-Clause"
 LIC_FILES_CHKSUM = "file://LICENSE;md5=2982272c97a8e417a844857ca0d303b1"
 
-SRC_URI = "git://github.com/CESNET/libyang.git;protocol=https;branch=devel"
+SRC_URI = "git://github.com/CESNET/libyang.git;protocol=https;nobranch=1"
 
 #PR ="r1"
 #SRCREV = "v${PV}"
diff -Naur ./tmp_orig/poky/meta-tsn-bsp/conf/machine/de-eval-board.conf ./tmp_mod_rt/poky/meta-tsn-bsp/conf/machine/de-eval-board.conf
--- ./tmp_orig/poky/meta-tsn-bsp/conf/machine/de-eval-board.conf	2021-03-15 14:28:31.000000000 +0000
+++ ./tmp_mod_rt/poky/meta-tsn-bsp/conf/machine/de-eval-board.conf	2021-07-28 15:51:41.122758637 +0100
@@ -7,7 +7,7 @@
 # disable rtc support
 MACHINE_FEATURES_BACKFILL_CONSIDERED += "rtc"
 
-IMAGE_FSTYPES = "wic.gz"
+IMAGE_FSTYPES = "wic.gz tar.gz"
 WKS_FILE = "sdimage-cyclone5-de-eval-board.wks"
 
 KMACHINE = "cyclone5"
diff -Naur ./tmp_orig/poky/meta-tsn-bsp/recipes-bsp/u-boot-scr/files/de-eval-board/u-boot.script ./tmp_mod_rt/poky/meta-tsn-bsp/recipes-bsp/u-boot-scr/files/de-eval-board/u-boot.script
--- ./tmp_orig/poky/meta-tsn-bsp/recipes-bsp/u-boot-scr/files/de-eval-board/u-boot.script	2021-03-15 14:28:31.000000000 +0000
+++ ./tmp_mod_rt/poky/meta-tsn-bsp/recipes-bsp/u-boot-scr/files/de-eval-board/u-boot.script	2021-07-28 15:51:41.122758637 +0100
@@ -3,13 +3,13 @@
 setenv bootimage zImage
 setenv fdtimage socfpga_cyclone5_de-eval-board.dtb
 setenv fpgaimage socfpga.rbf
-setenv fpgadata 0x3000000
+#setenv fpgadata 0x3000000
 
-echo --- Programming FPGA ---
+echo --- Not Programming FPGA ---
 
-load mmc 0:1 $fpgadata $fpgaimage
+#load mmc 0:1 $fpgadata $fpgaimage
 bridge disable
-fpga load 0 $fpgadata $filesize
+#fpga load 0 $fpgadata $filesize
 bridge enable
 
 
diff -Naur ./tmp_orig/poky/meta-tsn-bsp/recipes-kernel/linux/5.4/dts/socfpga_cyclone5_de-eval-board_default.dts ./tmp_mod_rt/poky/meta-tsn-bsp/recipes-kernel/linux/5.4/dts/socfpga_cyclone5_de-eval-board_default.dts
--- ./tmp_orig/poky/meta-tsn-bsp/recipes-kernel/linux/5.4/dts/socfpga_cyclone5_de-eval-board_default.dts	2021-03-15 14:28:31.000000000 +0000
+++ ./tmp_mod_rt/poky/meta-tsn-bsp/recipes-kernel/linux/5.4/dts/socfpga_cyclone5_de-eval-board_default.dts	2021-07-28 15:51:41.150758427 +0100
@@ -47,9 +47,9 @@
 		compatible = "snps,dwmac-mdio";
 
 		/* Micrel KSZ9031 */
-		hps_phy1: phy@3 {
+		hps_phy1: phy@4 {
 			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <0x3>;
+			reg = <0x4>;
 			rxc-skew-ps = <1680>;	/* 780 ps */
 			rxdv-skew-ps = <420>;	/* 0 ps */
 			txc-skew-ps = <1860>;	/* 960 ps */
@@ -102,9 +102,9 @@
 &i2c0 {
 	status = "okay";
 
-	hps1_eth_eeprom: eeprom@50 {
+	hps1_eth_eeprom: eeprom@51 {
 		compatible = "atmel,at24c02";
-		reg = <0x50>;
+		reg = <0x51>;
 	};
 };
 
diff -Naur ./tmp_orig/poky/meta-tsn-bsp/recipes-kernel/linux/linux-tttech-industrial_5.4.bb ./tmp_mod_rt/poky/meta-tsn-bsp/recipes-kernel/linux/linux-tttech-industrial_5.4.bb
--- ./tmp_orig/poky/meta-tsn-bsp/recipes-kernel/linux/linux-tttech-industrial_5.4.bb	2021-03-15 14:28:31.000000000 +0000
+++ ./tmp_mod_rt/poky/meta-tsn-bsp/recipes-kernel/linux/linux-tttech-industrial_5.4.bb	2021-07-28 15:55:36.216992574 +0100
@@ -1,6 +1,14 @@
 PR = "r0"
 
+LINUX_VERSION_PATCHLEVEL ?= "40-rt24"
+
 include linux-tttech-industrial_5.4.inc
 
+# patch it to 5.4.40-rt24
+SRC_URI += "file://Upgrade-to-kernel-version-5.4.40-rt24.patch"
+
 # machine specific kernel configuration fragment
 SRC_URI += "file://${MACHINE}.cfg"
+
+# basic rt-preempt configuration
+SRC_URI += file://preempt.cfg
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