AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

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ID 683707
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

1.4. Design Flow for the TSN Drive-on-Chip Design Example

Intel does not supply source files, images, configuration files but does describe how to create them.
  1. Download both the Drive-on-Chip application and TTTech TSN IP onto the FPGA.
  2. Store them in the EPCQ memory of the Cyclone V SoC Development board using a .jic format file. The .jic file is a combination of the .sof output file (product of the Intel Quartus Compilation) and an .hex file (product of the Drive-on-Chip software compilation). The Drive-on-Chip design runs on the Nios II soft processor using the µCOSII (Real Time OS) framework.
  3. Program the TTTech TSN IP into the FPGA and it uses the HPS within the Cyclone V SoC to run Linux and manage the TSN system. The Intel Quartus Prime compilation for the project produces handoff files. These are input of BSP editor (part of SoC EDS) to create an HPS preloader.
  4. Use this preloader image to create an SD card image for the HPS to boot-up Linux.
  5. Build an SD card image for the development board using the YOCTO project. TTTech customized the flow to meet its IP requirements and tools. YOCTO is a method for building customized embedded Linux distributions.
  6. Describe, by using recipes, the components of your system and produce a bootable SD card image (or files) as the product of the build. For more information, refer to the YOCTO PROJECT website. A Linux machine launches the YOCTO build, as it cannot build on a mounted NFS volume.
  7. Patch the YOCTO build to adapt it to Cyclone V SoC Development board.
  8. Use the design as a base to integrate the TSN drive-on-chip hardware in Intel Quartus Prime. For Smart Factory solutions, the Linux distribution of the TTTech IP reference design (5.4.40) can be patched with Linux RT-patch 5.4.40-rt24 HPS runs Linux, necessary daemons, TTTech TSN drivers, and any other high-level application you program.
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