AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

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ID 683707
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools

  1. In Intel Quartus Prime, click Tools > Nios II Software Build Tools for Eclipse.
  2. Set the workspace to <project_location>/software/
  3. In Nios II Eclipse, click File > Import…
  4. In the window expand General, Existing Projects into Workspace. then Browse... and click Select root directory.
    Figure 29. Import project into Nios II Software Build Tools
  5. Select the project directory and the bsp directory.
  6. In Nios II Eclipse GUI, right click into the BSP directory and click Nios II > BSP Editor…
  7. Check that the SOPC Information file is set to <project_location>/DOC_TANDEM_CVSX_NIOS_TSN_QSYS.sopcinfo
  8. In the Drivers tab, select enable_jtag_uart_ignore_fifo_full_error. This is the only non-default option to turn on.
  9. Click Generate.
  10. In the Nios II Eclipse SBT, right click in the BSP directory, click Nios II > Generate BSP. The BSP generates.
    If you see errors because of the TTTech TSN IP during the Nios II software compilation or BSP generation, create a separate Qsys system without the de_ip_solution_scv_0 block (TSN IP) and compile the Nios II using the .sopcinfo file.
  11. Apply the following changes in the source code <project_location/software/DOC_TANDEM_CVSX_NIOS_TSN>:
    • Inside /platform/common/platform.h add another family of device name for example: #define SYSID_CVSX_NIOS 6
    • The device family should match the System ID set in the 0x005046fe sysid_0 block in Qsys.
    • Add the definition to platform.c in the variable device_family_t and TANDEM_FAMILIES
    • Add the family in other locations where device_family definition might appear, for example in motor_task.c
    • Inside demo_cfg.h, change the ACDS_MAJOR_VERSION to 5 or any other number, but that matches the System ID's sixth digit (e.g. 0x005046fe).
  12. In Nios II Eclipse, right click in the project directory, and click Build Project.
  13. Generate the .hex file for the EPCQ memory that is in the .jic: right click in the project directory and click Make Targets > Build….
  14. In the window select mem_init_generate and click Build
The .hex file to include in the .jic file generation is in <project_location>/software/DOC_TANDEM_CVSX_NIOS_TSN/mem_init/epcq.hex
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