AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example

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ID 683707
Date 10/30/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example 2. Getting Started with the TSN for Drive-on-Chip Design Example 3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board 4. Running HPS Software for the TSN Drive-on-Chip Design 5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board 6. Running the Program 7. TSN Configuration Example 8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example A. Example .qsf for Pin Assignments and Attributes B. Top-level Verilog HDL File Example C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example D. Script to read and change MAC addresses from Cyclone V SoC EEPROM
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example x
1.1. Features of TSN for Drive-on-Chip Design Example 1.2. TSN for Drive-on-Chip Design Example General Description 1.3. Messages from the TSN Drive-on-Chip Design Example 1.4. Design Flow for the TSN Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example x
2.1. Hardware Requirements for the TSN for Drive-on-Chip Design Example 2.2. Software Requirements for the TSN for Drive-on-Chip Design Example 2.3. Configuring the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.4. Programming the FPGA for the TSN for Drive-on-Chip Design Example 2.5. Creating an SD Card Image for the TSN for Drive-on-Chip Design Example 2.6. Turning on the Cyclone V SoC Development Board for the TSN for Drive-on-Chip Design Example 2.7. Configuring the TSN IP
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board x
3.1. Changing File Names, Revision Name, and Target Device for the TSN Drive-on-Chip Design Example 3.2. Modifying the Drive-On-Chip Qsys System 3.3. Adding the TTTech TSN IP to the Qsys system 3.4. Connecting the TSN and Drive-on-Chip Subsystems 3.5. Compiling the Quartus Prime Design and Top-Level Module 3.6. Generating the Preloader 3.7. Generating a .jic file 3.8. Compiling the Drive-on-Chip Design Software in Nios II Software Build Tools 3.9. Launching a YOCTO Build 3.10. Building an SD Card Image for the TSN Drive-on-Chip Design Example 3.11. Changing MAC Addresses 3.12. Reading and Checking Physical Addresses on the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design x
4.1. Installing the Arm Compiler for Motor Control from Linux 4.2. Creating a Basic C Program for Motor Control 4.3. OPC UA PubSub based on open62541 4.4. Getting and Building open62541 4.5. Setting up Debug Sessions in DS-5
1. About the Time-Sensitive Networking for Drive-on-Chip Design Example
2. Getting Started with the TSN for Drive-on-Chip Design Example
3. Porting the Intel MAX 10 Drive-On-Chip design to the Cyclone V SoC Development Board
4. Running HPS Software for the TSN Drive-on-Chip Design
5. Connecting the Cyclone V SoC Development board to the Tandem 48 V Motion-Power board
6. Running the Program
7. TSN Configuration Example
8. Document Revision History for AN 957: Time-Sensitive Networking for Drive-on-Chip Design Example
A. Example .qsf for Pin Assignments and Attributes
B. Top-level Verilog HDL File Example
C. YOCTO Build Patch File (cvsx_doc_tsn_2_3-rt) for the TSN Drive-on-Chip Design Example
D. Script to read and change MAC addresses from Cyclone V SoC EEPROM

A. Example .qsf for Pin Assignments and Attributes

For the TSN Drive-on-Chip Design example. 
set_location_assignment PIN_AD27 -to global_reset_n
set_location_assignment PIN_A10 -to SD_MCLK
set_location_assignment PIN_AG7 -to INPUT_CURRENT_MDAT
set_location_assignment PIN_E8 -to INPUT_VOLTAGE_MDAT
set_location_assignment PIN_AF8 -to BOOST_DRV0_PWM_H
set_location_assignment PIN_D7 -to BOOST_DRV0_CURRENT_MDAT
set_location_assignment PIN_AG1 -to BOOST_DRV0_PWM_L
set_location_assignment PIN_D6 -to BOOST_DRV1_CURRENT_MDAT
set_location_assignment PIN_K12 -to DCBUS_CURRENT_MDAT
set_location_assignment PIN_C5 -to DCBUS_VOLTAGE_MDAT
set_location_assignment PIN_E4 -to DRV_SCLK
set_location_assignment PIN_J10 -to DRV_SOMI
set_location_assignment PIN_J9 -to DRV_SIMO
set_location_assignment PIN_E3 -to DRV0_SER_RX
set_location_assignment PIN_K7 -to DRV0_CSn
set_location_assignment PIN_E2 -to DRV0_SER_TX
set_location_assignment PIN_K8 -to DRV0_SER_CLK
set_location_assignment PIN_E1 -to DRV0_EN_GATE_P
set_location_assignment PIN_G12 -to DRV0_EN_GATE_N
set_location_assignment PIN_D1 -to HSMC_DRV0_PWM_UH
set_location_assignment PIN_G11 -to HSMC_DRV0_PWM_UL
set_location_assignment PIN_D2 -to HSMC_DRV0_PWM_VH
set_location_assignment PIN_J7 -to HSMC_DRV0_PWM_VL
set_location_assignment PIN_C2 -to HSMC_DRV0_PWM_WH
set_location_assignment PIN_H7 -to HSMC_DRV0_PWM_WL
set_location_assignment PIN_B2 -to DRV0_U_VOLTS_MDAT
set_location_assignment PIN_H8 -to DRV0_U_CURRENT_MDAT
set_location_assignment PIN_B1 -to DRV0_V_VOLTS_MDAT
set_location_assignment PIN_G8 -to DRV0_V_CURRENT_MDAT
set_location_assignment PIN_C3 -to DRV0_W_VOLTS_MDAT
set_location_assignment PIN_G10 -to DRV0_W_CURRENT_MDAT
set_location_assignment PIN_B3 -to DRV0_QR_A
set_location_assignment PIN_F10 -to DRV0_QHR_U
set_location_assignment PIN_AJ2 -to DRV0_QR_B
set_location_assignment PIN_AG2 -to DRV0_QHR_V
set_location_assignment PIN_AC12 -to DRV0_QR_Z
set_location_assignment PIN_AH3 -to DRV0_QHR_W
set_location_assignment PIN_F9 -to BOOST_STATUS
set_location_assignment PIN_F8 -to REGEN_STATUS
set_location_assignment PIN_D5 -to DRV1_SER_RX
set_location_assignment PIN_F11 -to DRV1_CSn
set_location_assignment PIN_C4 -to DRV1_SER_TX
set_location_assignment PIN_E11 -to DRV1_SER_CLK
set_location_assignment PIN_A6 -to DRV1_EN_GATE_P
set_location_assignment PIN_B6 -to DRV1_EN_GATE_N
set_location_assignment PIN_A5 -to HSMC_DRV1_PWM_UH
set_location_assignment PIN_B5 -to HSMC_DRV1_PWM_UL
set_location_assignment PIN_C7 -to HSMC_DRV1_PWM_VH
set_location_assignment PIN_E9 -to HSMC_DRV1_PWM_VL
set_location_assignment PIN_B7 -to HSMC_DRV1_PWM_WH
set_location_assignment PIN_D9 -to HSMC_DRV1_PWM_WL
set_location_assignment PIN_A9 -to DRV1_U_VOLTS_MDAT
set_location_assignment PIN_D11 -to DRV1_U_CURRENT_MDAT
set_location_assignment PIN_A8 -to DRV1_V_VOLTS_MDAT
set_location_assignment PIN_D10 -to DRV1_V_CURRENT_MDAT
set_location_assignment PIN_C8 -to DRV1_W_VOLTS_MDAT
set_location_assignment PIN_E12 -to DRV1_W_CURRENT_MDAT
set_location_assignment PIN_B8 -to DRV1_QR_A
set_location_assignment PIN_D12 -to DRV1_QHR_U
set_location_assignment PIN_C10 -to DRV1_QR_B
set_location_assignment PIN_F13 -to DRV1_QHR_V
set_location_assignment PIN_C9 -to DRV1_QR_Z
set_location_assignment PIN_E13 -to DRV1_QHR_W
set_location_assignment PIN_K14 -to DRV1_SER_TX_EN
set_location_assignment PIN_C13 -to DRV0_SER_TX_EN
set_location_assignment PIN_J12 -to VOLTAGE_FAULT
set_location_assignment PIN_D4 -to DRV0_FAULTn
set_location_assignment PIN_A4 -to CURRENT_FAULT
set_location_assignment PIN_A3 -to DRV1_FAULTn
set_location_assignment PIN_B13 -to GPIO_0
set_location_assignment PIN_A13 -to DRV1_RESOLVER_SSCS
set_location_assignment PIN_B12 -to DRV0_RESOLVER_SSCS
set_location_assignment PIN_C12 -to DRV1_RESOLVER_SCSB
set_location_assignment PIN_F15 -to DRV0_RESOLVER_SCSB
set_location_assignment PIN_B11 -to DRV1_RESOLVER_INHB
set_location_assignment PIN_F14 -to DRV0_RESOLVER_INHB
set_location_assignment PIN_E7 -to DRV1_RESOLVER_ERRHLD
set_location_assignment PIN_H15 -to DRV0_RESOLVER_ERRHLD
set_location_assignment PIN_E6 -to DRV1_RESOLVER_ERRSTB
set_location_assignment PIN_G15 -to DRV0_RESOLVER_ERRSTB
set_location_assignment PIN_AD12 -to HSMC_PRSNTn
set_location_assignment PIN_AG12 -to mem_a[14]
set_location_assignment PIN_AK8 -to mem_a[13]
set_location_assignment PIN_AK7 -to mem_a[12]
set_location_assignment PIN_AK9 -to mem_a[11]
set_location_assignment PIN_AJ9 -to mem_a[10]
set_location_assignment PIN_AH14 -to mem_a[9]
set_location_assignment PIN_AH13 -to mem_a[8]
set_location_assignment PIN_AK13 -to mem_a[7]
set_location_assignment PIN_AK12 -to mem_a[6]
set_location_assignment PIN_AH15 -to mem_a[5]
set_location_assignment PIN_AG15 -to mem_a[4]
set_location_assignment PIN_AJ12 -to mem_a[3]
set_location_assignment PIN_AH12 -to mem_a[2]
set_location_assignment PIN_AK14 -to mem_a[1]
set_location_assignment PIN_AJ14 -to mem_a[0]
set_location_assignment PIN_AK11 -to mem_ba[2]
set_location_assignment PIN_AJ11 -to mem_ba[1]
set_location_assignment PIN_AH10 -to mem_ba[0]
set_location_assignment PIN_AA14 -to mem_ck
set_location_assignment PIN_AA15 -to mem_ck_n
set_location_assignment PIN_AJ21 -to mem_cke
set_location_assignment PIN_AG23 -to mem_dm[1]
set_location_assignment PIN_AH17 -to mem_dm[0]
set_location_assignment PIN_AJ27 -to mem_dm[3]
set_location_assignment PIN_AK23 -to mem_dm[2]
set_location_assignment PIN_AF18 -to mem_dq[0]
set_location_assignment PIN_AE17 -to mem_dq[1]
set_location_assignment PIN_AG16 -to mem_dq[2]
set_location_assignment PIN_AF16 -to mem_dq[3]
set_location_assignment PIN_AH20 -to mem_dq[4]
set_location_assignment PIN_AG21 -to mem_dq[5]
set_location_assignment PIN_AJ16 -to mem_dq[6]
set_location_assignment PIN_AH18 -to mem_dq[7]
set_location_assignment PIN_AK18 -to mem_dq[8]
set_location_assignment PIN_AJ17 -to mem_dq[9]
set_location_assignment PIN_AG18 -to mem_dq[10]
set_location_assignment PIN_AK19 -to mem_dq[11]
set_location_assignment PIN_AG20 -to mem_dq[12]
set_location_assignment PIN_AF19 -to mem_dq[13]
set_location_assignment PIN_AJ20 -to mem_dq[14]
set_location_assignment PIN_AH24 -to mem_dq[15]
set_location_assignment PIN_AE19 -to mem_dq[16]
set_location_assignment PIN_AE18 -to mem_dq[17]
set_location_assignment PIN_AG22 -to mem_dq[18]
set_location_assignment PIN_AK22 -to mem_dq[19]
set_location_assignment PIN_AF21 -to mem_dq[20]
set_location_assignment PIN_AF20 -to mem_dq[21]
set_location_assignment PIN_AH23 -to mem_dq[22]
set_location_assignment PIN_AK24 -to mem_dq[23]
set_location_assignment PIN_AF24 -to mem_dq[24]
set_location_assignment PIN_AF23 -to mem_dq[25]
set_location_assignment PIN_AJ24 -to mem_dq[26]
set_location_assignment PIN_AK26 -to mem_dq[27]
set_location_assignment PIN_AE23 -to mem_dq[28]
set_location_assignment PIN_AE22 -to mem_dq[29]
set_location_assignment PIN_AG25 -to mem_dq[30]
set_location_assignment PIN_AK27 -to mem_dq[31]
set_location_assignment PIN_V17 -to mem_dqs[1]
set_location_assignment PIN_V16 -to mem_dqs[0]
set_location_assignment PIN_AK21 -to mem_reset_n

set_location_assignment PIN_AC18 -to clk_50
set_location_assignment PIN_AF14 -to clk_ddr3_100_p
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
set_global_assignment -name ENABLE_OCT_DONE ON

set_location_assignment PIN_H14 -to BOOST_DRV1_PWM_H
set_location_assignment PIN_AK2 -to LED[0]
set_location_assignment PIN_Y16 -to LED[1]
set_location_assignment PIN_W15 -to LED[2]
set_location_assignment PIN_AB17 -to LED[3]
set_location_assignment PIN_AA13 -to button[0]
set_location_assignment PIN_AB13 -to button[1]
set_location_assignment PIN_G13 -to BOOST_DRV1_PWM_L
set_location_assignment PIN_AF9 -to REGEN_EN_N

set_location_assignment PIN_AC20 -to mem_dqs[3]
set_location_assignment PIN_Y17 -to mem_dqs[2]
set_location_assignment PIN_AD19 -to mem_dqs_n[3]
set_location_assignment PIN_AA18 -to mem_dqs_n[2]
set_location_assignment PIN_W17 -to mem_dqs_n[1]
set_location_assignment PIN_W16 -to mem_dqs_n[0]
set_location_assignment PIN_AG17 -to mem_oct_rzqin

set_location_assignment PIN_AB15 -to mem_cs_n
set_location_assignment PIN_AH8 -to mem_ras_n
set_location_assignment PIN_AH7 -to mem_cas_n
set_location_assignment PIN_AJ6 -to mem_we_n
set_location_assignment PIN_AE16 -to mem_odt
set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_50
set_instance_assignment -name IO_STANDARD "1.5 V" -to clk_ddr3_100_p
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[13] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[13] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[14] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[14] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[15] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[15] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[16] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[16] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[16] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[17] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[17] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[17] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[18] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[18] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[18] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[19] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[19] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[19] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[20] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[20] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[20] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[21] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[21] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[21] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[22] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[22] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[22] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[23] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[23] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[23] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[24] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[24] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[24] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[25] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[25] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[25] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[26] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[26] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[26] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[27] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[27] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[27] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[28] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[28] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[28] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[29] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[29] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[29] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[30] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[30] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[30] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dq[31] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dq[31] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dq[31] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_dqs_n[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to mem_dqs_n[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dqs_n[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 4 -to mem_dqs_n[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cke[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cke[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 2 -to mem_ck[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to mem_ck_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to mem_ck_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name D5_DELAY 2 -to mem_ck_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ba[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_we_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_ras_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_cas_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_odt[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.5 V" -to mem_reset_n -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to mem_dm[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_dm[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[13] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[14] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[15] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[16] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[17] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[18] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[19] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[20] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[21] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[22] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[23] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[24] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[25] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[26] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[27] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[28] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[29] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[30] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dq[31] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dm[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs_n[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_dqs[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_a[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ba[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_we_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ras_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cas_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_cke[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_odt[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_ck_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to mem_reset_n -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name GLOBAL_SIGNAL OFF -to u_doc|mem_if_ddr3_emif_0|p0|umemphy|ureset|phy_reset_n -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u_doc|mem_if_ddr3_emif_0 -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "1.5 V" -to LED[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to LED[1]
set_instance_assignment -name IO_STANDARD "1.5 V" -to LED[2]
set_instance_assignment -name IO_STANDARD "1.5 V" -to LED[3]
set_instance_assignment -name IO_STANDARD "1.5 V" -to button[0]
set_instance_assignment -name IO_STANDARD "1.5 V" -to button[1]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_reset_n -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[10] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[11] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[12] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[13] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[13] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[14] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[14] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[3] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[4] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[5] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[6] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[7] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[8] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to mem_a[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_a[9] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name IO_STANDARD "SSTL-15" -to mem_oct_rzqin -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[2] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[1] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ba[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cs_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_ras_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_cas_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_we_n[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to mem_odt[0] -tag __DOC_TANDEM_MAX10_QSYS_mem_if_ddr3_emif_0_p0

set_location_assignment PIN_H19 -to enet_hps_gtx_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_gtx_clk
set_location_assignment PIN_B21 -to enet_hps_mdc
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_mdc
set_location_assignment PIN_E21 -to enet_hps_mdio
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_mdio
set_location_assignment PIN_G20 -to enet_hps_rx_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_rx_clk
set_location_assignment PIN_K17 -to enet_hps_rx_dv
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_rx_dv
set_location_assignment PIN_A21 -to enet_hps_rxd[0]
set_location_assignment PIN_B20 -to enet_hps_rxd[1]
set_location_assignment PIN_B18 -to enet_hps_rxd[2]
set_location_assignment PIN_D21 -to enet_hps_rxd[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_rxd
set_location_assignment PIN_A20 -to enet_hps_tx_en
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_tx_en
set_location_assignment PIN_F20 -to enet_hps_txd[0]
set_location_assignment PIN_J19 -to enet_hps_txd[1]
set_location_assignment PIN_F21 -to enet_hps_txd[2]
set_location_assignment PIN_F19 -to enet_hps_txd[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to enet_hps_txd
set_location_assignment PIN_A16 -to sd_clk
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_clk
set_location_assignment PIN_F18 -to sd_cmd
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_cmd
set_location_assignment PIN_G18 -to sd_dat[0]
set_location_assignment PIN_C17 -to sd_dat[1]
set_location_assignment PIN_D17 -to sd_dat[2]
set_location_assignment PIN_B16 -to sd_dat[3]
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to sd_dat
set_location_assignment PIN_E24 -to uart_rx
set_location_assignment PIN_D24 -to uart_tx
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_rx
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to uart_tx
set_location_assignment PIN_D22 -to i2c_scl_hps
set_location_assignment PIN_C23 -to i2c_sda_hps
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i2c_scl_hps
set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to i2c_sda_hps

set_location_assignment PIN_F26 -to ddr3_hps_a[0]
set_location_assignment PIN_G30 -to ddr3_hps_a[1]
set_location_assignment PIN_F28 -to ddr3_hps_a[2]
set_location_assignment PIN_F30 -to ddr3_hps_a[3]
set_location_assignment PIN_J25 -to ddr3_hps_a[4]
set_location_assignment PIN_J27 -to ddr3_hps_a[5]
set_location_assignment PIN_F29 -to ddr3_hps_a[6]
set_location_assignment PIN_E28 -to ddr3_hps_a[7]
set_location_assignment PIN_H27 -to ddr3_hps_a[8]
set_location_assignment PIN_G26 -to ddr3_hps_a[9]
set_location_assignment PIN_D29 -to ddr3_hps_a[10]
set_location_assignment PIN_C30 -to ddr3_hps_a[11]
set_location_assignment PIN_B30 -to ddr3_hps_a[12]
set_location_assignment PIN_C29 -to ddr3_hps_a[13]
set_location_assignment PIN_H25 -to ddr3_hps_a[14]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[4] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[5] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[6] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[7] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[8] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[9] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[10] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[11] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[12] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[13] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_a[14] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[0] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[1] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[2] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[3] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[4] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[5] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[5] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[6] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[6] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[7] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[7] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[8] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[8] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[9] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[9] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[10] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[10] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[11] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[11] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[12] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[12] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[13] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[13] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_a[14] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_a[14] -tag __hps_sdram_p0
set_location_assignment PIN_E29 -to ddr3_hps_ba[0]
set_location_assignment PIN_J24 -to ddr3_hps_ba[1]
set_location_assignment PIN_J23 -to ddr3_hps_ba[2]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_ba[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_ba[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_ba[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ba[0] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ba[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ba[1] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ba[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ba[2] -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ba[2] -tag __hps_sdram_p0

set_location_assignment PIN_M23 -to ddr3_hps_ck
set_instance_assignment -name D5_DELAY 2 -to ddr3_hps_ck -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_ck -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_ck -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_hps_ck -tag __hps_sdram_p0

set_location_assignment PIN_L23 -to ddr3_hps_ck_n
set_instance_assignment -name D5_DELAY 2 -to ddr3_hps_ck_n -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_ck_n -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_ck_n -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITHOUT CALIBRATION" -to ddr3_hps_ck_n -tag __hps_sdram_p0

set_location_assignment PIN_L29 -to ddr3_hps_cke
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_cke -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_cke -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_cke -tag __hps_sdram_p0

set_location_assignment PIN_H24 -to ddr3_hps_cs_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_cs_n -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_cs_n -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_cs_n -tag __hps_sdram_p0

set_location_assignment PIN_D30 -to ddr3_hps_ras_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_ras_n -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_ras_n -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_ras_n -tag __hps_sdram_p0

set_location_assignment PIN_E27 -to ddr3_hps_cas_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_cas_n -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_cas_n -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_cas_n -tag __hps_sdram_p0

set_location_assignment PIN_C28 -to ddr3_hps_we_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_we_n -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_we_n -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_we_n -tag __hps_sdram_p0

set_location_assignment PIN_P30 -to ddr3_hps_reset_n
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_reset_n -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_reset_n -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_reset_n -tag __hps_sdram_p0

set_location_assignment PIN_K23 -to ddr3_hps_dq[0]
set_location_assignment PIN_K22 -to ddr3_hps_dq[1]
set_location_assignment PIN_H30 -to ddr3_hps_dq[2]
set_location_assignment PIN_G28 -to ddr3_hps_dq[3]
set_location_assignment PIN_L25 -to ddr3_hps_dq[4]
set_location_assignment PIN_L24 -to ddr3_hps_dq[5]
set_location_assignment PIN_J30 -to ddr3_hps_dq[6]
set_location_assignment PIN_J29 -to ddr3_hps_dq[7]
set_location_assignment PIN_K26 -to ddr3_hps_dq[8]
set_location_assignment PIN_L26 -to ddr3_hps_dq[9]
set_location_assignment PIN_K29 -to ddr3_hps_dq[10]
set_location_assignment PIN_K27 -to ddr3_hps_dq[11]
set_location_assignment PIN_M26 -to ddr3_hps_dq[12]
set_location_assignment PIN_M27 -to ddr3_hps_dq[13]
set_location_assignment PIN_L28 -to ddr3_hps_dq[14]
set_location_assignment PIN_M30 -to ddr3_hps_dq[15]
set_location_assignment PIN_U26 -to ddr3_hps_dq[16]
set_location_assignment PIN_T26 -to ddr3_hps_dq[17]
set_location_assignment PIN_N29 -to ddr3_hps_dq[18]
set_location_assignment PIN_N28 -to ddr3_hps_dq[19]
set_location_assignment PIN_P26 -to ddr3_hps_dq[20]
set_location_assignment PIN_P27 -to ddr3_hps_dq[21]
set_location_assignment PIN_N27 -to ddr3_hps_dq[22]
set_location_assignment PIN_R29 -to ddr3_hps_dq[23]
set_location_assignment PIN_P24 -to ddr3_hps_dq[24]
set_location_assignment PIN_P25 -to ddr3_hps_dq[25]
set_location_assignment PIN_T29 -to ddr3_hps_dq[26]
set_location_assignment PIN_T28 -to ddr3_hps_dq[27]
set_location_assignment PIN_R27 -to ddr3_hps_dq[28]
set_location_assignment PIN_R26 -to ddr3_hps_dq[29]
set_location_assignment PIN_V30 -to ddr3_hps_dq[30]
set_location_assignment PIN_W29 -to ddr3_hps_dq[31]
set_location_assignment PIN_W26 -to ddr3_hps_dq[32]
set_location_assignment PIN_R24 -to ddr3_hps_dq[33]
set_location_assignment PIN_U27 -to ddr3_hps_dq[34]
set_location_assignment PIN_V28 -to ddr3_hps_dq[35]
set_location_assignment PIN_T25 -to ddr3_hps_dq[36]
set_location_assignment PIN_U25 -to ddr3_hps_dq[37]
set_location_assignment PIN_V27 -to ddr3_hps_dq[38]
set_location_assignment PIN_Y29 -to ddr3_hps_dq[39]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[4] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[5] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[6] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[7] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[8] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[9] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[10] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[11] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[12] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[13] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[14] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[15] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[16] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[17] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[18] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[19] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[20] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[21] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[22] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[23] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[24] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[25] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[26] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[27] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[28] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[29] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[30] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[31] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[32] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[33] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[34] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[35] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[36] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[37] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[38] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dq[39] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[0] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[1] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[2] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[3] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[4] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[4] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[5] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[5] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[5] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[6] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[6] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[6] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[7] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[7] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[7] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[8] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[8] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[8] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[9] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[9] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[9] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[10] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[10] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[10] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[11] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[11] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[11] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[12] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[12] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[12] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[13] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[13] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[13] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[14] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[14] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[14] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[15] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[15] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[15] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[16] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[16] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[16] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[17] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[17] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[17] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[18] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[18] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[18] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[19] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[19] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[19] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[20] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[20] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[20] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[21] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[21] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[21] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[22] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[22] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[22] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[23] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[23] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[23] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[24] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[24] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[24] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[25] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[25] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[25] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[26] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[26] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[26] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[27] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[27] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[27] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[28] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[28] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[28] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[29] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[29] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[29] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[30] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[30] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[30] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[31] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[31] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[31] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[32] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[32] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[32] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[33] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[33] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[33] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[34] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[34] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[34] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[35] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[35] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[35] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[36] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[36] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[36] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[37] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[37] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[37] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[38] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[38] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[38] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dq[39] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[39] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dq[39] -tag __hps_sdram_p0

set_location_assignment PIN_N18 -to ddr3_hps_dqs[0]
set_location_assignment PIN_N25 -to ddr3_hps_dqs[1]
set_location_assignment PIN_R19 -to ddr3_hps_dqs[2]
set_location_assignment PIN_R22 -to ddr3_hps_dqs[3]
set_location_assignment PIN_T24 -to ddr3_hps_dqs[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs[0] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs[1] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs[2] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs[3] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs[4] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[4] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs[4] -tag __hps_sdram_p0

set_location_assignment PIN_M19 -to ddr3_hps_dqs_n[0]
set_location_assignment PIN_N24 -to ddr3_hps_dqs_n[1]
set_location_assignment PIN_R18 -to ddr3_hps_dqs_n[2]
set_location_assignment PIN_R21 -to ddr3_hps_dqs_n[3]
set_location_assignment PIN_T23 -to ddr3_hps_dqs_n[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.5-V SSTL CLASS I" -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dqs_n[4] -tag __hps_sdram_p0

set_location_assignment PIN_H28 -to ddr3_hps_odt
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_odt -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_odt -tag __hps_sdram_p0
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr3_hps_odt -tag __hps_sdram_p0

set_location_assignment PIN_K28 -to ddr3_hps_dm[0]
set_location_assignment PIN_M28 -to ddr3_hps_dm[1]
set_location_assignment PIN_R28 -to ddr3_hps_dm[2]
set_location_assignment PIN_W30 -to ddr3_hps_dm[3]
set_location_assignment PIN_W27 -to ddr3_hps_dm[4]
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dm[0] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dm[1] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dm[2] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dm[3] -tag __hps_sdram_p0
set_instance_assignment -name PACKAGE_SKEW_COMPENSATION OFF -to ddr3_hps_dm[4] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[0] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[0] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[1] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[1] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[2] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[2] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[3] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[3] -tag __hps_sdram_p0
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_dm[4] -tag __hps_sdram_p0
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to ddr3_hps_dm[4] -tag __hps_sdram_p0

set_location_assignment PIN_D27 -to ddr3_hps_oct_rzqin
set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to ddr3_hps_oct_rzqin -tag __hps_sdram_p0

set_location_assignment PIN_H12 -to eth_mdio_tristate_0_mdio_mdc
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_tristate_0_mdio_mdc
set_location_assignment PIN_H13 -to eth_mdio_tristate_0_mdio_mdio
set_instance_assignment -name IO_STANDARD "2.5 V" -to eth_mdio_tristate_0_mdio_mdio

set_location_assignment PIN_AJ1 -to enet_dual_resetn
set_instance_assignment -name SLEW_RATE 0 -to enet_dual_resetn*

set_location_assignment PIN_Y24 -to deip_0_gmii_to_mii_0_mii_rx_clk
set_location_assignment PIN_Y23 -to deip_0_gmii_to_mii_0_mii_rx_dv
set_location_assignment PIN_AB23 -to deip_0_gmii_to_mii_0_mii_rxd[0]
set_location_assignment PIN_AA24 -to deip_0_gmii_to_mii_0_mii_rxd[1]
set_location_assignment PIN_AB25 -to deip_0_gmii_to_mii_0_mii_rxd[2]
set_location_assignment PIN_AE27 -to deip_0_gmii_to_mii_0_mii_rxd[3]
set_location_assignment PIN_AE28 -to deip_0_gmii_to_mii_0_mii_rx_er
set_location_assignment PIN_W25 -to deip_0_gmii_to_mii_0_mii_tx_clk
set_location_assignment PIN_AB22 -to deip_0_gmii_to_mii_0_mii_tx_en
set_location_assignment PIN_W20 -to deip_0_gmii_to_mii_0_mii_txd[0]
set_location_assignment PIN_Y21 -to deip_0_gmii_to_mii_0_mii_txd[1]
set_location_assignment PIN_AA25 -to deip_0_gmii_to_mii_0_mii_txd[2]
set_location_assignment PIN_AB26 -to deip_0_gmii_to_mii_0_mii_txd[3]

set_location_assignment PIN_AH30 -to deip_0_gmii_to_mii_1_mii_rx_clk
set_location_assignment PIN_AC28 -to deip_0_gmii_to_mii_1_mii_rx_dv
set_location_assignment PIN_AF29 -to deip_0_gmii_to_mii_1_mii_rxd[0]
set_location_assignment PIN_AF30 -to deip_0_gmii_to_mii_1_mii_rxd[1]
set_location_assignment PIN_AD26 -to deip_0_gmii_to_mii_1_mii_rxd[2]
set_location_assignment PIN_AC27 -to deip_0_gmii_to_mii_1_mii_rxd[3]
set_location_assignment PIN_V25 -to deip_0_gmii_to_mii_1_mii_rx_er
set_location_assignment PIN_AG30 -to deip_0_gmii_to_mii_1_mii_tx_clk
set_location_assignment PIN_W24 -to deip_0_gmii_to_mii_1_mii_tx_en
set_location_assignment PIN_AG27 -to deip_0_gmii_to_mii_1_mii_txd[0]
set_location_assignment PIN_AG28 -to deip_0_gmii_to_mii_1_mii_txd[1]
set_location_assignment PIN_AF28 -to deip_0_gmii_to_mii_1_mii_txd[2]
set_location_assignment PIN_V23 -to deip_0_gmii_to_mii_1_mii_txd[3]
Level Two Title